Transmission Gate Switches Research Articles

Dynamic coil switching strategies for significant efficiency increases in electromagnetic energy generators

The development of self-powering systems has been recognized as critical such that innovative stand-alone emerging technologies can operate sustainably from scavenged ambient energy. Electromagnetic generators (EMGs) using magnetic levitation architectures for mechanical vibration energy harvesting are a promising technology that can be tailored to specific needs and provide low-cost electric powering for both small-scale and large-scale devices. They also present non-complex design, with low maintenance requirements and can operate with stable performance for long periods of time. Despite these prominent features, their complex non-linear and hysteresis-based resonant characteristics makes performance optimization hard to achieve and still needs to be addressed as a function of the input excitation. Numerical and experimental results are here provided to demonstrate the effectiveness of a new concept of EMG that aims to dynamically adapt the coil-array architecture throughout its operation to ensure maximum harvested power and to optimize the transduction mechanism efficiency. The self-adaptive motion-driven levitation-based autonomously rearranges each coil independently as a function of the instantaneous time-varying characteristics of the levitating magnet (LM) position. The mechanism features two dynamic coil switching strategies: (i) on/off switching, by short circuiting, with transmission gate switches, the coils without influence on the electromotive force; and (ii) reversing polarity switching, to avoid the sum of electromotive forces cancels each other. Average output powers of 635 mW (up to ∼4.1 W of peak power) were obtained with only the 4-centre (out of 14) permanently active coils, while only 292 mW (up to 833 mW of peak power) were achieved with the 14-coils permanently connected under optimal load conditions and harmonic translational input excitations with 15 Hz frequency and 20 mm amplitude. However, the adaptive generator was able to provide an impressive average power output of 3 W under the same conditions. Up to 14-fold larger output average power and 5.5-fold larger electric efficiency demonstrate the potential of the proposed coil switching self-adaptation system for enhancing the total energy conversion from general widespread mechanical vibrations.

A 2.4 GHz Reconfigurable Cascode/Folded-Cascode Inductive Source Degenerated LNA With Enhanced OP1dB and OIP3 Over Gain Reduction

A 2.4 GHz reconfigurable cascode/folded-cascode inductive source degenerated LNA (ISDLNA) is proposed to implement the variable-gain functionality with enhanced output 1 dB compression point (OP1dB) and output third-order intercept point (OIP3) over the gain reduction, ensuring low noise figure (NF) of sub-1 dB at high gain mode. Depending on the channel condition, the LNA is designed to be operated as the cascode and folded-cascode ISDLNA through the digital switch control to have low NF of around 1 dB at high gain mode and high input P1dB (IP1dB) of greater than -5 dBm at low gain mode, respectively. To avoid the reliability issues caused by the overdriving control voltage of greater than the nominal supply voltage, the transmission gate switch is employed as the common gate stage of the cascode amplifier. In experiments, the proposed variable-gain LNA shows a power gain (S21), input return loss (S11), and NF of 11.8 dB, -31.8 dB, and 1.1 dB at high gain mode, and 5.0 dB, -14.4 dB, and 1.96 dB at low gain mode. In case of the linearity, the proposed LNA shows an IP1dB and input IP3 (IIP3) of -19.2 dBm and -5 dBm at high gain mode, and -5.1 dBm and +4.8 dBm at low gain mode, respectively. The power consumption for two operation modes is the same as 9.6 mW from a 1.2 V supply voltage.

Triple Sensing Current Margin for Maintainable MRAM Yield at Sub-100% Tunnel Magnetoresistance Ratio

Spin transfer torque magnetic random access memory (STT-MRAM) creates significant breakthroughs as a proper candidate of next-generation non-volatile memory (NVM). Although STT-MRAM achieves high endurance, low access latency, and power consumption, the yield issue remains one of the critical concerns in high-density and large-scale MRAM array design. In this article, a novel triple-current margin sensing amplifier (TM-SA) is proposed for maintainable MRAM yield based on the current-mode SA and transmission gate switches. The sensing current margin of the proposed TM-SA is three times enlarged compared to traditional current mean (CM)-SA and resistance mean (RM)-SA. With a seriously degraded tunnel magnetoresistance (TMR) ratio (sub-100%, as low as 10%), the maximum voltage margin is 4.6 times of conventional CM-SA and five times of RM-SA. Monte-Carlo simulation shows that sensing failure probability can be greatly alleviated with the proposed TM-SA. The performance of TM-SA with respect to voltage margin can be further improved than that of CM-SA and RM-SA.

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

<p>A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR.</p>

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width W P range of 3 to 35 µm the average W N / W P ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.

A digital library for a flexible low-voltage organic thin-film transistor technology

This paper presents the design, fabrication and characterization of digital logic gates, flip-flops and shift registers based on low-voltage organic thin-film transistors (TFTs) on flexible plastic substrates. The organic transistors are based on the p-channel organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) and have channel lengths as short as 5 μm and gate-to-contact overlaps of 20 μm. The organic TFT is modeled which allows us to simulate different logic gate architectures prior to the fabrication process. In this study, the zero-VGS, biased-load and pseudo-CMOS logic families are investigated, where their static and dynamic operations are modeled and measured. The inverter and NAND gates use channel length of 5 μm and operate with a supply voltage of 3 V. Static and dynamic master-slave flip-flops based on biased-load and pseudo-CMOS logic are designed, fabricated and characterized. A new design for biased-load dynamic flip-flops is proposed, where transmission gate switches are implemented using only p-channel transistors. 1-stage shift registers based on the new design and fabricated using TFTs with a channel length of 20 μm operate with a maximum frequency of about 3 kHz.

A high-speed latched comparator with low offset voltage and low dissipation

An ultra high-speed latched comparator using a controlled amount of positive feedback cell has been designed in TSMC 0.18 μm CMOS technique. Transmission gate (TG) switches are used to implement the preamplifier circuit. The use of TG switches results in a reduction in the power consumption of the high-speed comparator as well as clock feedthrough and the effect of charge injection. The simulation results demonstrate that it can work at 1.25 GHz suitable for high speed applications, and consumes 273.6 μW with a power supply of 1.8 V at 100 MHz and Monte Carlo simulation shows that the comparator has a low offset voltage approximately 0.499 mV.

Clock Feedthrough in CMOS Analog Transmission Gate Switches

An analysis of clock feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock feedthrough and a related model of a transmission gate switch are...

Transmission gate switch for ESD protection of RF pad

A novel transmission gate switch is proposed to effectively replace electrostatic discharge (ESD) protection resistors in CMOS I/O pads. The proposed circuit exhibits a very low on resistance, under normal operation, and a very high off resistance, in the case of ESD stresses. A triple-well CMOS implementation guarantees RF operation and enhanced ESD reliability.