Transition Faults Research Articles

Fixed-State Tests for Delay Faults in Scan Designs

One of the methods to reduce the power dissipation during scan shifting is based on holding the state inputs to the combinational logic of a circuit constant for the duration of a scan operation. We note that this method also allows a new type of two-pattern scan-based tests to be applied. We refer to these tests as fixed-state tests. These tests have several properties that make them effective as complements to skewed-load and broadside tests, and also allows them to be computed efficiently. We discuss these properties in the context of transition faults. We describe procedures for selecting the constant vector for the state inputs during a scan operation, and for generating fixed-state tests. We present experimental results to demonstrate the transition fault coverage improvements possible with these tests.

THE NON-SCAN DELAY TEST ENRICHMENT BASED ON RANDOM GENERATED LONG TEST SEQUENCES

The paper investigates the possibilities of application of random generated test sequences for at-speed testing of non-scan synchronous sequential circuits. Our research shows that relatively long random test sequences exhibit better transition fault coverages than tests produced by deterministic ATPG tools. We proposed an approach for dividing of long test sequences into subsequences. The application of the presented approach allows increasing the fault coverage of the initial random generated test sequence, minimizing the length of the test by eliminating subsequences that don’t detect new faults and determining, for particular circuit, the required length of the test subsequence which can be used for further construction of the test. The provided experimental results demonstrate the effectiveness of the proposed approach.

Factor of Randomness in Functional Delay Fault Test Generation for Full Scan Circuits

We investigated the influence of the random generation methods to the results of the functional delay test generation. There are the three possibilities: random generation of values 0 and 1 when the probability for the appearance of each value is 50% in every bit of test pattern; random generation of large integer values, which then are split into the sequences of 0’s and 1‘s according to the rules of the conversion of the decimal number to the binary number; anti-random generation when the presence of the earlier generated patterns is taken into account. We adopted the anti-random generation for the functional delay faults. The obtained results of the investigation indicate that the random generation has the direct influence to the results of the functional delay test generation. The largest coverage of transition fault is obtained when the anti-random generation is employed.

The Yakutat terrane: Dramatic change in crustal thickness across the Transition fault, Alaska

We present new constraints on the crustal structure of the Yakutat terrane and evidence of the role of the Transition fault in southern Alaska. The Yakutat terrane south of Yakutat Bay includes crystalline crust that is 24–27 km thick overlain by sedimentary units that are 4.5–7.5 km thick. The Yakutat terrane crustal thickness and velocity structure are consistent with an oceanic plateau origin. The southern edge of the Yakutat terrane is bounded by the Transition fault, which is imaged as a near-vertical fault zone ∼1 km wide. The Transition fault is coincident with a dramatic change in Moho depth from 32 km for Yakutat oceanic plateau crust to 11.5 km for Pacific Ocean crust occurring over a horizontal distance of 0–5 km. There is no evidence for underthrusting of the Pacific Ocean crust beneath the Yakutat terrane at the Transition fault. We argue that the Yakutat terrane formed on the Kula or Farallon plate and was later juxtaposed next to younger Pacific Ocean crust by the Transition fault.

Switching Activity as a Test Compaction Heuristic for Transition Faults

The switching activity of scan-based tests for delay faults is considered as a test compaction heuristic. Two test compaction processes based on the switching activity are described. The results of several experiments are presented where test sets consisting of tests with different switching activity are compared based on their size as well as coverage of untargeted faults. The results demonstrate that test sets where the tests have higher switching activity are smaller. Their untargeted fault coverage is comparable, and sometimes even higher, than that of larger test sets for the same target faults. To avoid overtesting due to high switching activity it is possible to consider functional broadside tests. For other types of tests it is possible to bound the switching activity such that it would not exceed that possible during functional operation.

Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage

Transition path delay faults were defined to capture the behavior of both small and large delay defects in a single fault model. The number of detectable transition path delay faults as defined earlier is the same or close to the number of conventional path delay faults that are detectable under the strong non-robust propagation conditions. When the weak non-robust propagation conditions are used, the number of detectable conventional path delay faults is significantly higher. Using what are called the hazard-based detection conditions for transition faults, we define detection conditions for transition path delay faults, under which the number of detectable faults is the same or close to the number of conventional path delay faults that are detectable under the weak non-robust propagation conditions. The fault model still captures the behavior of both small and large delay defects, but the number of detectable faults is significantly higher.

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes

At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this paper, we propose a comparison between the two testing schemes in terms of transition fault coverage and power consumption, in order to quantify the pros and cons of LOS with respect to LOC. This study shows that LOS exhibits higher performance in transition delay fault coverage and pattern count, and does not require a significant amount of extra power (with respect to LOC), especially in terms of peak power dissipation. These facts may represent convincing arguments for its wider use and development.

Incremental Solving Techniques for SAT-based ATPG

Automatic test pattern generation (ATPG) based on the Boolean satisfiability (SAT) problem has recently been proven to be a beneficial complement to traditional methods. Efficient SAT techniques yield a robust fault classification. In this paper, we present methodologies to improve the efficiency of SAT-based ATPG. First, we give a detailed run time analysis of a state-of-the-art SAT-based ATPG tool. By only taking circuit partitions into account and applying incremental SAT solving, both SAT instance generation and SAT instance solving can be accelerated and the robustness of the ATPG process is increased. Besides the significant run time reduction of SAT-based ATPG, the methodology can additionally be used to improve the test set quality. The proposed techniques are applied for the stuck-at and for the transition fault model. A set of large industrial designs is used to show the efficiency of the approach.

GENERATING FUNCTIONAL DELAY FAULT TESTS FOR NON-SCAN SEQUENTIAL CIRCUITS

The paper presents two functional fault models that are devoted for functional delay test generation for non-scan synchronous sequential circuits. These fault models form one joint functional fault model. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the length of clock sequence. The length of clock sequence is determined using the presented functional fault models. The experimental results demonstrate the superiority of the delay test patterns generated at the functional level using the introduced functional fault models against the transition test patterns obtained at the gate level by deterministic test pattern generator. The functional delay test generation method especially is useful for the circuits, when the long test sequences are needed in order to detect transition faults.

A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost

This paper presents a new method for improving transition fault coverage in hybrid scan testing. It is based on a novel test application scheme, in order to break the functional dependence of broadside testing. The new technique analyzes the automatic test pattern generation conflicts in broadside test generation and skewed-load test generation, and tries to control the flip-flops with the most influence on fault coverage. The conflict-driven selection method selects some flip-flops that work in the enhanced scan mode or skewed-load scan mode. And the conflict-driven reordering method distributes the selected flip-flops into different chains. In the multiple scan chain architecture, to avoid too many scan-in pins, some chains are driven by the same scan-in pin to construct a tree-based architecture. Based on the architecture, the new test application scheme allows some flip-flops to work in enhanced scan or skewed-load mode, while most of others to work in the traditional broadside scan mode. With the efficient conflict-driven selection and reordering schemes, fault coverage is improved greatly, which can also reduce test application time and test data volume. Experimental results show that fault coverage based on the proposed method is comparable that of enhanced scan.

Analysis of multibackground memory testing techniques

Analysis of multibackground memory testing techniquesMarch tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model—such as pattern sensitive faults—their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is one of such techniques. In this case a selected March test is run many times. Each time it is run with new initial conditions. One of the conditions which we can change is the initial memory background. In this paper we compare the efficiency of multibackground tests based on four different algorithms of background generation.

Diagnosis of path delay faults based on low-coverage tests

Fault diagnosis processes consider the fact that a circuit fails a test as carrying more information than if the circuit passes a test. As a result, tests that detect smaller numbers of faults are likely to result in more accurate fault diagnosis. We study the existence of low-coverage tests, which detect small numbers of faults, for stuck-at faults, transition faults and path delay faults. The study shows that such tests are prevalent for path delay faults. We discuss the use of low-coverage tests for diagnosis of path delay faults, and describe a procedure for generating low-coverage tests for path delay faults.

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests

We define a new type of detection conditions for delay faults, referred to as hazard-based detection conditions, to enhance the coverage of delay faults using the standard scan test application methods. Some delay faults, including irredundant faults, may be undetectable under the conventional detection conditions. These faults may be detectable under the hazard-based detection conditions. The use of hazard-based detection conditions thus improves the delay fault coverage achievable for a circuit. We consider transition faults under standard scan for the study in this paper.

RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences

Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. However, they suffer from low defect coverage since they are mostly derived in practice from existing design-verification test sequences. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a DFT method that uses the register-transfer level (RTL) output deviations metric to select observation points for an RTL design and a given functional test sequence. Simulation results for six ITC?99 circuits show that the proposed method outperforms two baseline methods for several gate-level coverage metrics, including stuck-at, transition, bridging, and gate-equivalent fault coverage. Moreover, by inserting a small subset of all possible observation points using the proposed method, significant fault coverage increase is obtained for all benchmark circuits.

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

Since scan testing is not based on the function of the circuit, but rather the structure, it is considered to be both a form of over testing and under testing. Moreover, it is important to test VLSIs using the given function. Since the functional specifications are described explicitly in the FSMs, high test quality is expected by performing logical fault testing and timing fault testing. This paper proposes a fault-dependent test generation method to detect specified fault models completely and to increase defect coverage as much as possible under the test length constraint. We present experimental results for MCNC'91 benchmark circuits to evaluate bridging fault coverage, transition fault coverage, and statistical delay quality level and to show the effectiveness of the proposed test generation method compared with a stuck-at fault-dependent test generation method.

TEST QUALITY ASSESSMENT BASED ON SMALL DELAY DEFECTS

The quality of delay testing focused on small delay defects is not known when transition fault model is used. The paper presents a method that evaluates the quality of the delay test according to the covered paths of the circuit and constructs the paths, which could be used as the input to the path delay test generator. All the constructed paths are testable. The complexity of the circuit has no direct impact on the path construction. The path construction is based on the information provided by TetraMAX transition fault simulator. The transition fault simulator forms a text file that contains the complete information on the propagation of the transitions along the lines of the circuit. The experimental results demonstrate the ability to assess the quality of the delay test according to the covered paths.

Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits

In enhanced-scan circuits, a two-pattern test < t i , t j > for a transition fault can be obtained by using a test t j that detects a stuck-at fault, and preceding it by a test t i that activates another stuck-at fault. Thus, test generation for transition faults can be done by combining pairs of stuck-at tests. This provides an alternative to deterministic test generation, as well as reduces the test storage requirements for transition fault tests. We study the possibility of generating scan-based tests for transition faults in standard-scan circuits in a similar way, by combining pairs of stuck-at tests. Since it is not always possible to obtain a standard-scan test that is equivalent to a two-pattern test < t i , t j > based on stuck-at tests t i and t j , it is not always possible to guarantee that the combination of t i and t j will detect a transition fault. To compensate for this, it is necessary to try combinations of different stuck-at test pairs, resulting in an increased simulation effort to compute effective standard-scan tests. Our focus in this work is on reducing this simulation effort by reducing the number of stuck-at test pairs that need to be considered.

LPTest: a Flexible Low-Power Test Pattern Generator

This paper presents a low power test pattern generator, LPTest, that minimizes the peak power consumption during the shift and capture cycles for scan-based stuck-at and transition fault testing. LPTest incorporates both power-aware ATPG and low-power X-filling techniques to achieve higher power reduction. Its enabling technique is a power estimation method which assesses the lower-bounds of the shift-in, shift-out, and capture powers of a partially specified test pattern. The lower-bound estimation method is utilized in LPTest's ATPG engine, dynamic compaction, and X-filling. LPTest has been validated using ISCAS89 benchmark circuits. When considering all cycles, LPTest achieves better than 22% peak WSA (weighted switching activity) reduction for stuck-at and transition faults compared to a commercial ATPG with high merge ratio and random-fill options. Meanwhile, the average power reduction is better than 43%. When only capture power is of concern, LPTest attains more than 46% WSA reduction for stuck-at and transitions.

High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability

A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay-fault coverage is usually attributed to the fact that a two-pattern test for delay testing cannot be delivered to modules under test in two consecutive cycles. To solve the problem, we propose an HLTS method that ensures that valid test pairs can be sent to each module through synthesized circuit hierarchy. Experimental results show that this method achieves 100% fault coverage for transition faults in modules; in contrast, the fault coverage in circuits synthesized by a left-edge-algorithm-based allocation algorithm is rather poor. The area overhead due to this method ranges from 1% to 10% for 16-b datapath circuits. On the other hand, hierarchical test patterns cannot provide good delay-fault coverage for faults in interconnection structure and registers. The reason is that some control sequences required for delay-fault detection cannot be provided by the controller. We propose two design-for-testability insertion methods to deal with this problem. Experimental results show that, on the average, at least 11% higher delay-fault coverage is achieved by these methods.

Functional delay test generation based on software prototype

The paper presents two methods of functional delay test development based on the software prototype as well as the results of their application to benchmark circuits. The first method is used to construct the functional delay test on the base of a pin pair test generated at the functional level for detection of stuck-at faults at the gate-level. The constructed test is a single input transition test. The latter appears to be quite large. Therefore, we provide the method for compacting it. The compacted single input transition test becomes a multi-input transition test. The second method is used to generate a multi-input transition test. The generated functional test pattern pairs possess function-robust and/or function-non-robust properties. The introduction of the function-non-robust property enriches the functional delay test. The presented test construction approach based on the software prototype allows obtaining a functional delay test, which detects the transition faults at the gate-level of a circuit quite completely.