Transistor-level Description Research Articles

Design Considerations of a Nonvolatile Accumulator Based 8-bit Processor

The rise of the Internet of Things (IoT) and the constant growth of portable electronics have leveraged the concern with energy consumption due to the use of batteries in these devices. The nonvolatile memory (NVM) emerged as a solution to mitigate the problem due to its ability to retain data on sleep mode without a power supply. Nonvolatile processors (NVPs), in turn, may further improve energy saving, by making use of nonvolatile flip-flops (NVFFs) that store system state in parallel, allowing the device to be turned off when idle and resume execution instantly after power-on. This work describes the initial steps to implement a nonvolatile version of Neander, a hypothetical processor created for educational purposes. First, we implemented Neander in Register Transfer Level (RTL), separating the combinational logic from the sequential elements. Then, the latter were replaced by transistor-level descriptions ofvolatile flip-flops. We then validated this implementation by employing a mixed-signal simulation over a set of benchmarks. Results shown the expected behavior for the whole instruction set. Then, we implemented MTJ-based non-volatile flip-flops in circuit-level, using an open-source MTJ model. These elements were exhaustive validated using electrical simulations. With these results, we intend to carry on the implementation and fully equip our processor with nonvolatile features such as instant wake up.

Subcircuit Pattern Recognition in Transistor Level Circuits

The paper presents a computer program for automatically extracting the hierarchy of a large-scale digital circuit from its transistor-level description derived from the layout of VLSI circuit. The considered problem arises in VLSI layout verification as well as in the circuit reengineering. The proposed subcircuit recognition algorithm extracts functional level structure from transistor-level circuit collecting transistors into gates without using any predefined cell library. The algorithm comes from a SPICE like network description and realizes three-step process. First, a structural approach in which gate structures are recognized as channel connected sequences of transistors is used. Then channel connected sequences of transistors which implement CMOS gates are searched for. And finally the method of subcircuit pattern recognition is used to gather the rest sequences of transistors into minimal number of classes of identical functional blocks. The presented algorithm has been implemented as a program in C++ and tested using practical transistor-level circuits.

RCA on FPGAs Designed by RTL Design Methodology and Wave-Pipelined Operation

Field-programmable gate arrays (FPGAs) are used in various systems with reconfigurable functions. Conventional FPGAs have been developed using a transistor level description for minimizing routing delay. Although FPGAs developed with a register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors advanced their development. They should be shown to operate with practical throughput. For this purpose, circuits on these device need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) was designed and the throughput of the RCA was evaluated. The resulting throughput was applicable to network processors. Additionally, a wave-pipelined operation without changing the RCA revealed that the problem of routing delay in FPGA developed by RTL methodology was mitigated. The contributions of this paper are to clarify that a 4-bit adder can be implemented on FPGAs and their throughput can be improved by wave-pipelined operations.

Present and future of I/O-buffer behavioral macromodels

Modern Signal and Power Integrity (SI/PI) verification flows rely on accurate models for complex I/O-buffers that drive and receive electrical signals on high-speed channels. The sheer density of modern integrated circuits makes detailed transistor-level descriptions computationally cumbersome to the point where they become unusable for systemlevel simulations. Fortunately, transistor-level descriptions may be replaced with more compact representations that approximate the input/output buffers behavior with considerable accuracy while providing a simulation speedup of several orders of magnitude. Known as behavioral models, surrogate models or macromodels, these computationally efficient equivalents have become a de-facto industry standard in SI/ PI simulations. This paper presents an overview of the stateof- the-art in I/O-buffer behavioral modeling, introducing the main features of both standard and emerging solutions. Open issues and future research directions are also discussed.

RF Input Matching Design for Closed-Loop Direct Delta–Sigma Receivers

Emerging digital-intensive receiver architectures require new methods for input matching design. In particular, closed-loop $\Delta \Sigma$ -based receivers inject discrete-time global feedback to the RF low-noise amplifier (LNA) output. When using feedback LNA topologies with local internal feedback, receiver input matching thus no longer depends only on analog LNA characteristics, but also on the transfer function of the full receiver chain. This paper proposes a systematic input matching design method for such receivers. We demonstrate how this method is applied to the recently introduced active direct delta–sigma receiver (DDSR). We also show that global $\Delta \Sigma$ feedback in the DDSR counteracts the effects of the local feedback of the LNA on receiver input impedance, and how this can be used to improve receiver performance. A generic DDSR input impedance model is thus developed to facilitate input matching design. The related design method does not require transistor-level description of the post-LNA blocks, but relies instead only on easily obtainable system-level properties. A design example and measurements of a 0.7–2.7-GHz DDSR in 40-nm CMOS verify a good match between the theoretical and experimental results.

A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package

Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considered. It is found that IBIS models demonstrate some limits for this application, mainly due to the poor stabilization of the supply voltage rails. An example highlighting the IBIS model limits is given. A simple hand analysis of the phenomenon is performed, from which we derive a simple solution to the problem, consisting in an improvement of the structure of the IBIS model. Simulations run making use of the improved models show a much better accuracy of the signal shapes, within 5% of the simulations run with a state-of-the-art transistor level description of the buffers.

Behavioral Thermal Modeling for Microwave Power Amplifier Design

System-level models simplify the analysis of complex RF systems, such as transmission-reception modules, by expressing global input-output relationships. However, the development of high RF power models for nonlinear subsystems requires the prediction of the distortion induced by low-frequency memory effects such as self-heating effects. In this framework, we present a new electrothermal behavioral model for power amplifiers. This global model is based on the coupling between a behavioral electrical model derived from the transistor-level description of the amplifier and a thermal reduced model. This model, implemented into a circuit simulator, allows to predict the impact of the thermal effects in pulsed RF mode thanks to an envelope transient analysis. This approach has also been validated by measurements.

Extending gate-level diagnosis tools to CMOS intra-gate faults

A comprehensive solution to the intra-gate diagnosis problem, including intra-gate bridging and stuck-open faults is provided. The work is based on a local transformation technique that allows transistor-level faults to be diagnosed by the commonly available gate-level fault diagnosis tools without having to deal with the complexity of a transistor-level description of the whole circuit. Three transformations are described: one for stuck-open faults, one for intra-gate resistive-open faults and one for intra-gate bridging faults. Experimental work has been conducted at NXP Semiconductors using the NXP diagnosis tool – FALOC. A number of real diagnosis results from the wafer testing data including both stuck-open faults and intra-gate bridging faults have confirmed the effectiveness of this new method.

A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor

In this presentation, we will deal with verification of custom designed embedded memories. Using our paradigm, one can abstract the behavior of a memory block by a couple of artifacts--one representing its contents, and another representing its interface. We make use of the well known behavioral model known as the Efficient Memory Model (EMM) [29, 30] to represent contents of memories. We provide a methodology using which the behavior of a switch (or equivalently, transistor) level device can be specified using parameterized regular expressions. These entities can be used to abstractly describe the behavior of a bunch of switches that represent the interface of a memory. An automaton that we construct out of an abstract memory interface definition represents an abstraction of the memory interface itself. We show that such an automaton also forms a transducer that is a simulation model in a symbolic simulation environment. An EMM representing a memory core in conjunction with a transducer representing its interface is used as an abstraction of a complete memory during our automatic verification process.We also present a language formalism using which we show that the outputs from the transducers that are generated from the abstract specifications are weaker than or equal to the outputs defined by the regular expressions, in a partially ordered output space. We show that although the regular expressions are defined over exact and legal input strings, the transducers computed from them can provide outputs even when provided with weak or illegal input strings. This is an absolute necessity in order to have the capability to produce outputs when treated as a reactive system embedded in a symbolic simulation environment. Thus, we show that the simulation model generated by our technique is an conservative approximation of the corresponding abstract specification.We present a simple theory of composition that can be used to compose different simulation models used in our technique. Memories consisting of several ports result into several user-provided abstract specifications, which in turn result into several transducers that can be composed into a single transducer. That transducer in turn can be composed to a simulation model of an EMM. Our simple theory of composition also enables one to compose the abstract state space a memory core along with its ports with the concrete state space of the circuitry surrounding the memory core. We have shown that the composite simulation model representing the complete circuit has a partially ordered state space that (a) forms a complete lattice, and (b) that has a monotonic state transition function, that makes it suitable for being used in a symbolic simulation environment making use of Symbolic Trajectory Evaluation (STE) [27].The verification paradigm used is STE. For Motorola high performance microprocessors, switch level models are hand designed assuming that corresponding RTLs are golden models. Therefore, checking of equivalence between the two models is of absolute necessity as the RTL needs to be predictive of silicon behavior. We have developed a tool based on the proposed technique and used it to check that RTL descriptions of custom memories have been correctly implemented by transistor level descriptions of the same, augmented with abstract specifications of their cores. Our example circuits were taken from the state of the art Motorola MPC7450 microprocessor, a Motorola PowerPC. Experimental evidence testify to the effectiveness of the technique in catching subtle bugs in data path circuitry.

False-noise analysis using logic implications

Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes the assumption that all aggressing nets can simultaneously switch in the same direction. This creates a worst- case noise pulse on the victim net that often leads to false noise violations. In this article we present a new approach that uses logic implications to identify the maximum set of aggressor nets that can inject noise simultaneously under the logic constraints of the circuit. We propose an approach to efficiently generate logic implications from a transistor-level description and propagate them in the circuit using ROBDD representations. We propose a new method for lateral propagation of implications and also show how tristate gates and high-impedance signal states can be handled using tristate implications. We then show that the problem of finding the worst-case logically feasible noise can be represented as a maximum weighted independent set problem and show how to efficiently solve it. Initially, we restrict our discussion to zero-delay implications, which are valid for glitch-free circuits, and then extend our approach to timed implications. The proposed approaches were implemented in an industrial noise analysis tool and results are shown for a number of industrial test cases. We demonstrate that a significant reduction in the number of noise failures can be obtained from considering the logic implications as proposed in this article, underscoring the need for false-noise analysis.

Reconfigurable analogue systems: The pulse-based approach

The paper presents new research into programmable analogue and mixed signal VLSI. The reported advances are placed in context of commercially produced field programmable analogue arrays whose performance and limitations are discussed. The novel approach reported uses digital pulses to encode analogue signal information. This is done by modulating the width of a digital pulse. Two pulse width coding schemes are described. The operating of the signal processing scheme is outlined without recourse to detailed transistor level descriptions. Results from working prototype VLSI devices are produced demonstrating the capability of the technique for implementing analogue sampled data, mixed signal and continuous time processing circuits. The suitability of the technique to future VLSI technology trends is highlighted.