Transistor Implementation Research Articles

Power Reversible Comparator Circuits 180 nm Technology

This article explains design of reversible comparator circuits using GDI and TG in 180 nm technology, because of number of applications of reversible comparator [8] circuits in different fields. In this article, by combining CMOS-GDI circuit and CMOS-TG Circuits, we have implemented transistor of reversible gates. It has been observed that, usage of these techniques saves power and area as compare to CMOS implementation. GDI circuits provide some measure of enhanced hazard tolerance and are more suitable for low voltage operation [14]. Here transistor implementation of reversible gates is done by using Tanner tools and H-spice tools.

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

Reversible logic is becoming one of the best emerging design approaches for future computation of reversible logic having its more application in low power application. This logic is applied in the quantum computers, optical computing, communication and nanotechnology. In reversible logic approach generates the garbage input/output. In this paper design of proposed reversible logic multiplexer with garbage input/output, that the low power, area design technique are using that is the Gate -Diffusion -Input (GDI cell) in this dynamic component of power is reduced, In GDI cell PMOS is not connected to supply voltage VDD and NMOS is not connected to the GND.GDI circuits provide some measure issues of enhanced hazard tolerance and low voltage operation of reversible logic circuits. In this paper propose a novel application of GDI (Gate-Diffusion Input) circuits to Reversible logic multiplexer with its Garbage input and output. The new proposed design technique will consume less power than the other traditional gate. In recent years ago reversible logic circuit is less power dissipation. This GDI cell technique reduces the power of the circuit, delay, PowerDelay Product (PDP) and it also reduced frequency. The device scaling is limited by the power dissipation are more optimize in terms of delay, power supply, frequency , duty cycle, frequency jitter bandwidth of the signal and also demonstrated the noise of the circuit. The proposed reversible logic design. the GDI is effective in low power, low leakage current and lower Delay, The transistor implementation of the proposed gates is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm technology, some of the trade-offs are made in the design to improve the efficiency.

Graphene oxide gate dielectric for graphene-based monolithic field effect transistors

We report unique electrical anisotropy and dielectric properties of graphene oxide (GO) thin films, which allow facile implementation of GO-based monolithic field effect transistors (FETs). We demonstrate that exposure of GO films to hydrogen plasma leads to self-limiting reduction of only the uppermost layers such that a semiconductor-on-insulator type heterostructure is realized. In such heterostructures, the reduced uppermost layers and the unmodified bulk GO layers serve as the channel and gate dielectric components, respectively, of a thin film FET.

High on/off ratio field effect transistors based on exfoliated crystalline SnS2 nano-membranes

We report the implementation of field effect transistors based on exfoliated nano-membranes of a layered two-dimensional semiconductor SnS2, which exhibit an on/off ratio exceeding 2 × 106 and a carrier mobility of ∼1 cm2 V−1 s−1. The results demonstrate the great potential of SnS2, a layered semiconductor with finite band gap, as the building block for future nanoelectronic applications complementary to graphene-based materials with zero or small band gaps.

Power Efficient Variability Compensation Through Clustered Tunable Power-Gating

Power efficiency and variability, currently, are the main aspects of concern of nanometer-scale CMOS technology. Both issues have been widely studied and described in the literature, and various options for their independent management are available. Unfortunately, their exacerbation on sub-40 nm processes will require new design solutions for concurrent optimization. This paper moves towards this objective, and presents a new, fully-automated, design methodology, based on the Monitor and Control paradigm, able to improve the timing yield of a system making use of traditional power-gating (PG) as a knob for controlling power consumption and performance. In particular, the design and implementation of tunable-size sleep transistors is described, as well as a methodology for inserting them in a row-based layout. In order to keep under control both area and power overhead that come from the insertion of the sleep transistors, this paper also proposes a new strategy for clustering and power-gating only the timing critical cells. The experimental results are extremely promising. In fact, the proposed approach guarantees 100% of the timing yield with average leakage-power savings of about 29%.

Dynamic Analysis of a General Class of Winner-Take-All Competitive Neural Networks

This paper studies a general class of dynamical neural networks with lateral inhibition, exhibiting winner-take-all (WTA) behavior. These networks are motivated by a metal-oxide-semiconductor field effect transistor (MOSFET) implementation of neural networks, in which mutual competition plays a very important role. We show that for a fairly general class of competitive neural networks, WTA behavior exists. Sufficient conditions for the network to have a WTA equilibrium are obtained, and rigorous convergence analysis is carried out. The conditions for the network to have the WTA behavior obtained in this paper provide design guidelines for the network implementation and fabrication. We also demonstrate that whenever the network gets into the WTA region, it will stay in that region and settle down exponentially fast to the WTA point. This provides a speeding procedure for the decision making: as soon as it gets into the region, the winner can be declared. Finally, we show that this WTA neural network has a self-resetting property, and a resetting principle is proposed.

Ambipolar organic transistors and near-infrared phototransistors based on a solution-processable squarilium dye

Implementation of organic transistors in low-end, large-volume microelectronics depends, greatly, on the level of performance that can be achieved, but also on the compatibility of the technology with low-cost processing methodologies. Here we examine the suitability of a family of solution-processable zwitterionic molecules, so-called squarilium dyes, for the fabrication of organic ambipolar transistors and their application in (opto)electronic circuits. Ambipolar organic semiconductors and transistors are interesting because they could deliver performance characteristics (i.e. noise margins and signal gain) similar to that of complementary logic, but with the fabrication simplicity associated with unipolar logic (i.e. single semiconductor material and single type of metal electrodes). By designing squarilium dyes with appropriate electrochemical characteristics we demonstrate single-layer organic transistors that exhibit ambipolar charge transport with balanced electron and hole mobilities. By integrating a number of these ambipolar transistors we are also able to demonstrate complementary-like voltage inverters with wide noise margin and high signal gain. Another interesting feature of the squarilium dyes studied here is their strong absorption in the near-infrared (NIR) region of the electromagnetic spectrum. By exploring this interesting property we are able to demonstrate NIR light-sensing ambipolar organic transistors with promising operating characteristics.

Indium Gallium Arsenide Based Non-Volatile Memory Devices with Site-Specific Self-Assembled Germanium Quantum Dot Gate

AbstractThis paper presents the implementation of indium gallium arsenide field-effect transistors (InGaAs FETs) as non-volatile memory using lattice-matched II-VI gate insulator and quantum dots of GeOx-cladded Ge as the floating gate. Studies have been done to show the ability of II-VI materials to act as a tunneling gate material for InGaAs based FETs, and GeOx-cladded Ge quantum dots having the ability to store charges in the floating gate of a memory device. Proposed structure of the InGaAs device is presented.

Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters

The future of all kinds of applications that require a submilliwatt consumption strictly depends on the capability to meet design specifications at the minimum power costs. While several computer-aided-design tools are present to estimate the power consumption of modern ICs at transistor level, it is very difficult to predict the power at higher level. Given the reduced time-to-market of modern communication devices, it is very often needed to have accurate power estimations prior to the transistor-level design. Allocating a too conservative power budget to a block implies a possible poor tradeoff between the specifications of building blocks that constitute the system and their power consumption. For future power-constrained wireless devices (like wireless nodes in sensor networks), it is very important to have high-level models which can help the designer with the initial high-level choices without going into transistor-level design. One of the important blocks in modern communication devices, particularly for spread-spectrum systems, is the frequency synthesizer. In this paper, the first power-consumption model for an ultralow-power ROM-based direct digital frequency synthesizer has been developed, which can help the designer in the power optimization at a high level prior to transistor implementation.

Ferroelectric polymer gate on AlGaN∕GaN heterostructures

There has been much investigation into the implementation of field effect transistors; however, a commercial device is still not available. An attempt is made here to develop a ferroelectric gate device using an Al0.3Ga0.7N∕GaN heterostructure with a two dimensional electron gas (2DEG). The ferroelectric copolymer poly(vinylidene fluoride∕trifluoroethylene) [P(VDF∕TrFE)] was chosen as a gate material due to advantages such as its small dielectric constant and low crystallization temperature in comparison with the perovskite ferroelectrics. A P(VDF∕TrFE) layer was successfully deposited onto an Al0.3Ga0.7N∕GaN heterostructure without degrading the transport properties of the 2DEG. The polarization reversal in the gate was proved by piezoelectric scanning force microscopy. With this structure, it was possible to demonstrate the ferroelectric gate operation when modulating the transport properties of the 2DEG due to the stable reversal of the spontaneous polarization in the gate. Transport measurements in combination with piezoelectric scanning probe microscopy enable an insight into the physical origin of the retention loss in the system.

Switching voltage, dynamic power dissipation and on-to-off conductance ratio of a spin field effect transistor

The metal-insulator-semiconductor (MIS) and high electron mobility transistor (HEMT) implementations of the spin field effect transistor (SpinFET) proposed by Datta and Das are considered. In both configurations, the SpinFET's switching voltage (for switching on or off) and power dissipation are found to be larger than those of the traditional MISFET or HEMT if the channel length is ≤90 nm. This is a consequence of the fact that spin orbit interaction strengths in semiconductors are too weak to impart any significant advantage to the SpinFET. The issue of non-ideal spin injection and detection at the source and drain contacts is also considered. The SpinFET's on-to-off conductance ratio rapidly degrades with decreasing spin injection/detection efficiency, dropping from infinity (for a one-dimensional channel) to as low as ∼9.5, if the spin injection/detection efficiency drops from 100% to 90%. The transconductance has a quadratic dependence on the spin injection efficiency. These analyses are valid at arbitrary temperatures.

Use of laser drilling in the manufacture of organic inverter circuits

Inverter circuits have been made by connecting two high-quality pentacene field-effect transistors. A uniform and pinhole-free 900 nm thick polyimide gate-insulating layer was formed on a flexible polyimide film with gold gate electrodes and partially removed by using a CO2 laser drilling machine to make via holes and contact holes. Subsequent evaporation of the gold layer results in good electrical connection with a gold gate layer underneath the gate-insulating layer. By optimization of the settings of the CO2 laser drilling machine, contact resistance can be reduced to as low as 3 ohms for 180 microm square electrodes. No degradation of the transport properties of the organic transistors was observed after the laser-drilling process. This study demonstrates the feasibility of using the laser drilling process for implementation of organic transistors in integrated circuits on flexible polymer films.

A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption

This work describes a method for analysis of voltage-to-current converters (V-I converters or transconductors) and a novel V- I converter circuit with significantly improved linearity. The new circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third- and fifth-order harmonic distortion components in the transconductor characteristics. An evaluation of the optimal circuit dimensioning is shown. Simple and robust design rules are derived for the chosen operation conditions. The transistor implementation is presented and a prototype V- I converter is realized in a digital 0.18-/spl mu/m CMOS technology. The measured spurious-free dynamic range is 75 dB in a frequency band of 10 MHz. The circuit occupies less than 0.02 mm/sup 2/ and dissipates 360 /spl mu/W.

A physically based analytic model of FET Class-E power amplifiers-designing for maximum PAE

In this paper, we present a new Class-E power-amplifier model. Through a physically based analysis, our novel approach yields closed-form expressions for input, output, and dc power. These expressions yield the important figures-of-merit [gain, drain efficiency, and power-added efficiency (PAE)]. Using standard device parameters, design optimization for maximum PAE follows directly from the analysis and applies to bath integrated and discrete transistor implementations. For integrated designs, the optimal FET aspect ratio can be determined, given the design variables of the Class-E output network (output power, frequency, supply voltage, and loaded-Q of the output resonator). In a discrete transistor application, the Class-E network can be optimized for one of the design variables. The detrimental effects of the device parasitics on the amplifier's performance at UHF and microwave frequencies are accounted for in the model and explained in this paper. We verified the validity of the model by comparing our computed values against those from simulations using an optimized 0.5-/spl mu/m CMOS level-3 SPICE model.

Enzyme transistor circuits

The authors explore the possibility of constructing extremely high-density computing architectures using molecular electronics technology. By employing the specificity of biological molecules, such as enzymes, new integrated circuit architectures which are essentially free from interconnection problems could be constructed. To clarify the proposed concept, the authors present a functional model of a basic biomolecular switching device called an ‘enzyme transistor’. The enzyme transistor is, in a sense, an artificial catalyst which selects a specific substrate molecule and transforms it into a specific product. Using this primitive function, various wire-free computing circuits can be realised: examples include biochemical amplifiers for analogue signal processing and basic digital circuits. Addressing the implementation issue, the authors also propose bioelectronic implementation of enzyme transistors.

Stability of a class of directionally sensitive asymmetric nonlinear neural networks

Asymmetrically connected inhibitory shunting networks are believed to occur in many areas of the brain. One such area is the visual system; these networks are found useful in explaining many peripheral visual phenomena. This paper examines a class of asymmetrically connected networks for stability and uniqueness of outputs; both time-invariant and moving inputs are considered. Under different sets of constaints upon the network characteristics and operating region, it is possible to obtain: • • bounded-input-bounded-output stability of the solutions; • • stability and uniqueness of the output to any input for a network of finite extent, with time-invariant inputs giving time-invariant outputs; • • localization of edge effects on a finite network, and stability and uniqueness of the output to any input for a network of infinite extent, with time-invariant or traveling-wave inputs giving time-invariant or traveling-wave outputs respectively. The constraints required for these three sets of characteristics are successively more stringent. The most interesting constraints are those required for localization of edge effects on a finite network; they are not satisfied by a network in which the output from each node is obtained by sharply thresholding the node potential. However, they can be satisfied if the network operates in a relatively low signal region, below saturation of the outputs. An example of a network which does satisfy the constraints is given by certain field effect transistor (FET) implementations.

Motion processing using asymmetric shunting lateral inhibitory networks

Asymmetrically connected inhibitory shunting networks are believed to occur in many areas of the brain, including the visual system; they can explain many peripheral visual phenomena. This paper illustrates their usefulness in motion detection, and compares details of their performance with experimental results. Two stimuli are considered: drifting gratings and jumping bars. An elementary motion detector (EMD) is defined, consisting of a pair of opposite-directed asymmetric inhibitory networks. A frequency-space expansion (equivalent to a Volterra-Wiener expansion) is used to examine the EMD's response to a drifting grating. The EMD can be tuned to independent spatial and temporal frequencies: by summing the outputs of a number of EMDs, a velocity-tuned network is obtained. This velocity-tuned network is very well suited to certain field effect transistor (FET) implementations. Since the network is nonlinear, the response to a drifting grating does not fully characterize its behaviour. The response to a jumping bar stimulus is also examined. Two animals are considered: *Cats: the work of Emerson et al on the response of directionally selective (DS) complex cells in cat visual cortex to a white noise signal. *Flies: the work of Franceschini et al on the response of the fly H1 cell to stimulation of two neighbouring receptor cells, and that of Horridge and Marcelja on the fly H1 response to various jumping bar and edge stimuli. Agreement with all three of these experiments cannot be expected, because the results for the two animals are not consistent. There are two main differences: *Time development of the velocity-tuned signal: for the fly H1 cell this generally consists of two sharp (ON and OFF) responses to the second presentation of the bar signal, while for the cat DS cell a more slowly varying signal is observed. *Response to two presentations of the bar signal in the same position (i.e., a 'jumping bar' that jumps zero distance): for the fly H1 cell there is generally no response, while the cat DS cell responds significantly. The velocity-tuned network agrees well with the results for the cat DS cells.

Verity—A formal verification program for custom CMOS circuits

In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current-generation processors and the necessity for manual designer intervention throughout the design process, proving design correctness is a major concern. In this paper we discuss Verity, a formal verification program for symbolically proving the equivalence between a high-level design specification and MOS transistor-level implementation. Verity applies efficient logic comparison techniques which implicitly exercise the behavior for all possible input patterns. For a given register-transfer level (RTL) system model, which is commonly used in present-day methodologies, Verity validates the transistor implementation with respect to functional simulation and verification performed at the RTL level.

Breakdown voltage in LDMOS transistors using internal field rings

The optimization of the floating-ring parameters and the breakdown voltage of a lateral DMOS (LDMOS) transistor using a single floating ring is presented. A first-order analytical approach is presented, showing the upper limit of the position of the ring, with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is also presented. The results, which support the analytical approach, allow the use of simple design rules for the implementation of high-voltage LDMOS transistors on a thick epitaxial layer. It is shown that improvements of breakdown voltage is obtained if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specific relationship. With a single ring, the breakdown voltage increases from 170 to 280 V for the same device area and to over 480 V if the area is allowed to increase by 25%.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modulation Doped Si/SiGe Heterostructures

ABSTRACTAn overview of SiGe-based, modulation doped heterostructures is given. Strained layer handling, a prerequisite for realizing both n- and p-type devices, Is treated in terms of band engineering. The main emphasis is put on recent results obtained with high-electron mobility n-type Si/SiGe structures. Hall, Shubnikov-deHaas, and cyclotron resonance measurements are presented. The thermal stability of the heterostructures and the dopant distribution are treated with respect to device applications. Room temperature and 77K dc-measurements on very recent modulation doped field effect transistor (MODFET) implementations using implanted source/drain contacts are discussed. Device concepts with n- and p-type MODFETs combined in a superior complementary layout (CMODFET) are proposed.