Transistor Arrays Research Articles

Inkjet‐Printed, Wafer‐Scale Organic Schottky‐Gate Transistors toward Single‐Battery‐Driven Integrated Logic

AbstractOrganic field‐effect transistors switched by insulated gates are the most essential building blocks, while usually plagued with degraded gate control arising from complicated dielectric engineering. Subsequently, the resulting large supply voltage and power consumption remain an essential issue for portable electronics driven by a single battery of only 1.5 V. Herein, wafer‐scale organic Schottky‐gate transistor arrays using inkjet‐printed few‐layer organic semiconducting crystals are reported. The transistors exhibit steep switching characteristics with an average subthreshold swing of 55 mV per dec and high signal amplification efficiency over 45 S A‐1, attributed to efficient Schottky gating and enhanced charge injection. Thereafter, high‐gain inverters are successfully demonstrated with an ultralow power consumption of only 800 pW; also, they are integrated as 1 V driven sequential logic circuits. A coplanar double‐gate geometry is also introduced for low‐voltage, single‐device AND logic. Therefore, the work opens new avenues toward the sustainable advancement in single‐battery‐driven, ultralow‐power organic electronics.

Integrated Logic Circuits Based on Wafer-Scale 2D-MoS2 FETs Using Buried-Gate Structures.

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) materials, such as molybdenum disulfide (MoS2), stand out due to their atomically thin layered structure and exceptional electrical properties. Consequently, they could potentially become one of the main materials for future integrated high-performance logic circuits. However, the local back-gate-based MoS2 transistors on a silicon substrate can lead to the degradation of electrical characteristics. This degradation is caused by the abnormal effect of gate sidewalls, leading to non-uniform field controllability. Therefore, the buried-gate-based MoS2 transistors where the gate electrodes are embedded into the silicon substrate are fabricated. The several device parameters such as field-effect mobility, on/off current ratio, and breakdown voltage of gate dielectric are dramatically enhanced by field-effect mobility (from 0.166 to 1.08 cm2/V·s), on/off current ratio (from 4.90 × 105 to 1.52 × 107), and breakdown voltage (from 15.73 to 27.48 V) compared with a local back-gate-based MoS2 transistor, respectively. Integrated logic circuits, including inverters, NAND, NOR, AND, and OR gates, were successfully fabricated by 2-inch wafer-scale through the integration of a buried-gate MoS2 transistor array.

Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer.

This article presents a low-noise high-power-efficiency analog front-end (AFE) for capacitive-micromachined-ultrasonic transducers (CMUT). Implemented in 28-nm CMOS technology, the proposed AFE features three-stage continuous time-gain compensation (TGC) embedded in both trans-impedance amplifiers (TIAs) and an analog beamformer to provide a large compensation range with no extra power-consumption cost. The use of noise cancellation and capacitive feedback optimizes the noise performance of TIAs. The first stage of the TGC is built in the TIA by adjusting the positive and negative resistance loads, which are composed of voltage-controlled transistor arrays. An all-pass passive network is used as the delay unit of the analog beamformer, meanwhile achieving the second TGC stage. Phase shift for all frequency components in the ultrasound pass-band is manifested as a delay to the echoes. The third stage of the TGC is merged with a summing unit, which is a closed-loop amplifier with variable resistance feedback. The design takes into account the ability to handle large signals and power consumption, with TIA and beamforming operating at voltages of 2.5 V and 0.9 V, respectively. Experimental results show that the proposed AFE achieves a 2.11 pA/√Hz input-referred noise (IRN) at the 5 MHz center frequency of the echoes while consuming only 1.02 mW/channel. A total exponential TGC range of 60 dB with continuous ranges of 12 dB, 24 dB, and 24 dB assigned to three stages has been verified for this work.

12-inch growth of uniform MoS2 monolayer for integrated circuit manufacture.

Two-dimensional (2D) semiconductors, such as transition metal dichalcogenides, provide an opportunity for beyond-silicon exploration. However, the lab to fab transition of 2D semiconductors is still in its preliminary stages, and it has been challenging to meet manufacturing standards of stability and repeatability. Thus, there is a natural eagerness to grow wafer-level, high-quality films with industrially acceptable scale-cost-performance metrics. Here we report an improved chemical vapour deposition synthesis method in which the controlled release of precursors and substrates predeposited with amorphous Al2O3 ensure the uniform synthesis of monolayer MoS2 as large as 12 inches while also enabling fast and non-toxic growth to reduce manufacturing costs. Transistor arrays were fabricated to further confirm the high quality of the film and its integrated circuit application potential. This work achieves the co-optimization of scale-cost-performance metrics and lays the foundation for advancing the integration of 2D semiconductors in industry-standard pilot lines.

Molecular Doping Modulation and Applications of Structure-Sorted Single-Walled Carbon Nanotubes: A Review.

Single-walled carbon nanotubes (SWCNTs) that have a reproducible distribution of chiralities or single chirality are among the most competitive materials for realizing post-silicon electronics. Molecular doping, with its non-destructive and fine-tunable characteristics, is emerging as the primary doping approach for the structure-controlled SWCNTs, enabling their eventual use in various functional devices. This review provides an overview of important advances in the area of molecular doping of structure-controlled SWCNTs and their applications. The first part introduces the underlying physical process of molecular doping, followed by a comprehensive survey of the commonly used dopants for SWCNTs to date. Then, it highlights how the convergence of molecular doping and structure-sorting strategies leads to significantly improved functionality of SWCNT-based field-effect transistor arrays, transparent electrodes in optoelectronics, thermoelectrics, and many emerging devices. At last, several challenges and opportunities in this field are discussed, with the hope of shedding light on promoting the practical application of SWCNTs in future electronics.

UV-converted heterogeneous wettability surface for the realization of printed micro-scale conductive circuits

Achieving high precision in the fabrication of electronic circuits through additive manufacturing requires breaking the resolution limit of traditional printing processes. To address this challenge, we have developed a novel approach that involves preparing a heterogeneous wetting surface using a light-sensitive NBE-acrylate resin. By creating differences in surface energy on the substrate, we can limit the spread of the ink and surpass the limitations of conventional processes, achieving a printing resolution of 5 μm. The NBE-acrylate resin can be cross-linked under white LED light illumination (with λ > 400 nm) to yield a hydrophobic surface, which can be converted to a hydrophilic surface by UV light illumination (λ = 254 nm). The photochemical reaction of the NBE-acrylate resin under different light irradiation was confirmed by Fourier transform infrared spectroscopy (FTIR) and atomic force microscope (AFM) microforce measurements. In combination with a photomask, patterned heterogeneous wettability surfaces were prepared, which can be utilized for printing precision electronic circuits. Micrometer-scale printed circuits with a low line-to-space (L/S) of 5/50 and 10/10 μm were successfully achieved by optimizing the ink formulation, which is significantly beyond the printing resolution. In the end, fully printed thin film transistor arrays based on semi-conducting carbon nanotubes were achieved, which showed higher charge carrier mobilities of 1.89–4.31 cm2 s−1 V−1 depending on the channel width, demonstrating the application of this precision printed technique.

Ultrathin, Flexible, and Reusable Silicon Shadow Masks Manipulated via Transfer Printing

Stencil lithography is a facile patterning technique that offers a potential solution to the limitations of conventional photolithography. However, several critical factors such as enhanced pattern resolution, ability to pattern on nonplanar surfaces, and multilayer patterning should further be addressed to extend the applications of stencil lithography. This study presents a novel ultrathin silicon shadow mask which is flexible, reusable, and able to be precisely aligned and manipulated through transfer printing. The small thickness of the silicon shadow mask inherently provides it with the enhanced resolution patterning on both planar and nonplanar surfaces. To highlight these attractive benefits, substrates are patterned with metal deposition as well as by etching in a multilayer configuration. Moreover, it is found that the pattern resolution which is degraded as the shadow mask is repeatedly coated with metal and becomes warped can be restored after the mask cleaning procedure, demonstrating its effective reusability. Finally, as a device‐level application, top contact/bottom gate organic thin film transistor arrays are fabricated on both planar and curved surfaces using the shadow mask. These results show the promise of stencil lithography as a versatile and reliable high resolution patterning method for various applications by exploiting the presented ultrathin silicon shadow mask.

High-Resolution Spatial Mapping of Pressure Distribution by a Flexible and Piezotronics Transistor Array

High-Resolution Spatial Mapping of Pressure Distribution by a Flexible and Piezotronics Transistor Array

Fabrication of Large‐Area Organic Thin Film Transistor Array with Highly Uniform Water‐Borne Polyimide Gate Dielectric via Green Solvent‐Engineered Bar‐Coating Process

AbstractHere, the utilization of a highly uniform water‐borne polyimide (W‐PI) thin film as a gate dielectric layer for large‐scale organic thin film transistors (OTFTs) exceeding 100 cm2 is presented, employing the bar‐coating technique. The W‐PI thin films are obtained uniformly over a large area by systematically manipulating the surface tension of the water‐soluble poly(amic acid) salts (W‐PAAS) solution using alcohol as a co‐solvent in a “Green” process. The thickness of the W‐PI thin film is precisely controlled within the range of tens to hundreds of nanometers by adjusting key parameters, including the concentration of the W‐PAAS solution, wire diameter, and bar‐coating speed. As a result, 500 pentacene‐based OTFTs are successfully fabricated on a 10 × 10 cm2 substrate, utilizing a 280 nm thick W‐PI gate dielectric film. These devices exhibit excellent uniformity, with field‐effect mobility of 0.20 ± 0.02 cm2 V−1 s−1. Furthermore, the fabrication of electronic devices using an environmental‐friendly bar‐coating method on large‐area flexible substrates is demonstrated. This study highlights the considerable potential of eco‐friendly W‐PI thin films as dielectric materials, offering advantages such as cost‐effectiveness and high efficiency for reliable industrial applications.

Large‐Scale N‐Type FET and Homogeneous CMOS Inverter Array Based on Few‐Layer MoTe2

Abstract2D MoTe2 is regarded as a favorable candidate for semiconductor nanoelectronics integration. Chemical‐vapor‐deposition‐grown MoTe2 usually presents p‐type characteristics. In order to realize basic electronic units like complementary metal‐oxide‐semiconductor (CMOS) inverter, controllable fabrication of p‐ and n‐type transistors at large scale is of vital importance. Here, large‐scale MoTe2 n‐channel field‐effect transistor (n‐FET) arrays are successfully fabricated with seamless coplanar metallic 1T′‐WTe2 contacts to reduce contact resistance. High‐k HfO2 serves as a gate dielectric and its atomic‐layer‐deposition (ALD) process causes an n‐doping effect on the 2H‐MoTe2 channel. The FETs perform typical n‐type characteristics with average electron density and on/off ratio of ≈1.7 × 1013 cm−2 and 2.1 × 104, respectively. Furthermore, large‐scale homogeneous CMOS inverter arrays are fabricated, showing clear logic swing with low power consumption (≈0.4 nW) and high device yield (≈92%). Notably, their voltage transfer characteristics exhibit small hysteresis, and they work well after being kept in air for 16 months, indicating high device stability. The statistical results show that both the n‐FETs and CMOS inverters have high uniformity and reliability in performance. Significantly, this fabrication method is free from transfer processes and compatible with traditional silicon technology. This work paves the way for the application of few‐layer MoTe2 in semiconductor nanoelectronics integration.

Fabrication of p-type 2D single-crystalline transistor arrays with Fermi-level-tuned van der Waals semimetal electrodes

High-performance p-type two-dimensional (2D) transistors are fundamental for 2D nanoelectronics. However, the lack of a reliable method for creating high-quality, large-scale p-type 2D semiconductors and a suitable metallization process represents important challenges that need to be addressed for future developments of the field. Here, we report the fabrication of scalable p-type 2D single-crystalline 2H-MoTe2 transistor arrays with Fermi-level-tuned 1T’-phase semimetal contact electrodes. By transforming polycrystalline 1T’-MoTe2 to 2H polymorph via abnormal grain growth, we fabricated 4-inch 2H-MoTe2 wafers with ultra-large single-crystalline domains and spatially-controlled single-crystalline arrays at a low temperature (~500 °C). Furthermore, we demonstrate on-chip transistors by lithographic patterning and layer-by-layer integration of 1T’ semimetals and 2H semiconductors. Work function modulation of 1T’-MoTe2 electrodes was achieved by depositing 3D metal (Au) pads, resulting in minimal contact resistance (~0.7 kΩ·μm) and near-zero Schottky barrier height (~14 meV) of the junction interface, and leading to high on-state current (~7.8 μA/μm) and on/off current ratio (~105) in the 2H-MoTe2 transistors.

Study of Large-area Flexible Transistor Array Fabrication

In recent years, the rapid preparation of transistor devices and the control of manufacturing costs have been the focus of researchers. Conventional transistor semiconductor films are usually applied by spin coating or magnetron sputtering. However, the spin coating method tends to cause material waste. Based on this, a method of screen printing semiconductor layers is proposed. In this paper, P3HT ink was obtained by dissolving a mixture of P3HT and ethyl cellulose in a toluene solution. The screen printing technique was used to successfully obtain the semiconductor layer, which in turn successfully printed the transistor array. The dielectric layer is the screen-printed ionic gel and the electrode is vaporized gold electrode, resulting in a 100% success rate of transistors. The operating performance of the device is more stable than that of the spin-coating method, and the switching ratio of the obtained device is stable above 104 when the gate voltage is -3–3 V, -4–4 V, and -5–5 V, respectively. This approach offers a new way of thinking about flexible printed electronics.

Achieving tissue-level softness on stretchable electronics through a generalizable soft interlayer design

Soft and stretchable electronics have emerged as highly promising tools for biomedical diagnosis and biological studies, as they interface intimately with the human body and other biological systems. Most stretchable electronic materials and devices, however, still have Young’s moduli orders of magnitude higher than soft bio-tissues, which limit their conformability and long-term biocompatibility. Here, we present a design strategy of soft interlayer for allowing the use of existing stretchable materials of relatively high moduli to versatilely realize stretchable devices with ultralow tissue-level moduli. We have demonstrated stretchable transistor arrays and active-matrix circuits with moduli below 10 kPa—over two orders of magnitude lower than the current state of the art. Benefiting from the increased conformability to irregular and dynamic surfaces, the ultrasoft device created with the soft interlayer design realizes electrophysiological recording on an isolated heart with high adaptability, spatial stability, and minimal influence on ventricle pressure. In vivo biocompatibility tests also demonstrate the benefit of suppressing foreign-body responses for long-term implantation. With its general applicability to diverse materials and devices, this soft-interlayer design overcomes the material-level limitation for imparting tissue-level softness to a variety of bioelectronic devices.

Scalable biomimetic sensing system with membrane receptor dual-monolayer probe and graphene transistor arrays.

Affinity-based biosensing can enable point-of-care diagnostics and continuous health monitoring, which commonly follows bottom-up approaches and is inherently constrained by bioprobes' intrinsic properties, batch-to-batch consistency, and stability in biofluids. We present a biomimetic top-down platform to circumvent such difficulties by combining a "dual-monolayer" biorecognition construct with graphene-based field-effect-transistor arrays. The construct adopts redesigned water-soluble membrane receptors as specific sensing units, positioned by two-dimensional crystalline S-layer proteins as dense antifouling linkers guiding their orientations. Hundreds of transistors provide statistical significance from transduced signals. System feasibility was demonstrated with rSbpA-ZZ/CXCR4QTY-Fc combination. Nature-like specific interactions were achieved toward CXCL12 ligand and HIV coat glycoprotein in physiologically relevant concentrations, without notable sensitivity loss in 100% human serum. The construct is regeneratable by acidic buffer, allowing device reuse and functional tuning. The modular and generalizable architecture behaves similarly to natural systems but gives electrical outputs, which enables fabrication of multiplex sensors with tailored receptor panels for designated diagnostic purposes.

Roll-to-roll gravure printed large-area flexible carbon nanotube synaptic photogating transistor arrays for image recognitions

The development of novel large-area flexible optoelectronic synaptic devices is of great interest for visual neuromorphic computing. In this paper, we have successfully manufactured 33 × 34 flexible carbon nanotube synaptic photogating transistor arrays via the roll-to-roll gravure printing technology using the mixture of photosensitive rhodamine 6G and poly(vinylidene fluoride-co-hexa-fluoropropylene) as the composite dielectric layer. The resulting thin-film transistor devices exhibit excellent electrical properties with high Ion/Ioff (>105), the maximum carrier mobility (10.71 cm2V−1s−1) and low operating voltage (−1.5 V∼ 0.5 V), and excellent optoelectronic synaptic properties, which are capable of performing not only the excitatory postsynaptic current and paired pulse facilitation but also complex biological synaptic functions such as optical writing and electrical erasure, dynamic learning and forgetting processes, and Pavlov's dog experiment. Significantly, the ultralow energy consumption per light spike event as low as 0.03 fJ can be achieved under the pulse UV light illumination. Moreover, according to the trend that the LTP/LTD curve conforms to the concave function, we successfully embed the specific update rules of our synaptic devices into the generative adversarial network (GAN) that can generate high-quality (7680 × 4096 pixels) images, which is impossible for the human eye to distinguish the difference between the original labels and real labels.

Effect of Large-Area Exfoliation and Etching on the Electrical Behavior of Transition-Metal Dichalcogenide Field-Effect Transistors

Large-area layer transfer was used to fabricate multilayer transition-metal dichalcogenide (TMDC) thin-film transistor (TFT) arrays with areas of (40 × 40 μm2) from single-crystal flakes. The effects of plasma etching of the TFT backchannel surface and bulk defects in the layers on the electrical performance and stability of the n-channel depletion-mode TFTs were investigated. Few-layer structures (∼3 monolayers) were fabricated using a dry etching process to thin multilayer (∼60–90 nm thick) TMDC structures. The etching improved the threshold voltage of the TFTs, resulting in a positive threshold voltage shift of +40 V after etching the backchannel, correlating to a bulk trap density of approximately 1 × 1016 cm–3 eV–1 per monolayer. Etching the MoS2 surface resulted in a threshold voltage shift of 0.2 V per nanometer of MoS2 removed (for MoS2 thicknesses >15 nm). For MoS2 layers etched to <15 nm, the threshold voltage changed to ∼1.8 V per nanometer. An observed degradation of the carrier transport and electrical stability of these samples were found to be due to the proximity of the etched surface approaching the active channel region of the device. The results reveal the performance trade-offs of fabricating large-area arrays of few-layer TMDC TFTs using a mechanical exfoliation and dry etching approach.

81‐1: Invited Paper: Highly stretchable backplane technologies for deformable display applications

Stretchable displays are a promising technology for developing new styles of deformable display applications. Here we develop two stretchable backplane technologies for future display applications. We first propose a highly stretchable metal‐oxide island thin‐film transistor array with an acrylic adhesive structure. We then construct a stretchable light‐emitting diode array containing stretchable through‐hole interconnects with printed stretchable conductors.

Synaptic Transistor Arrays Based on PVA/Lignin Composite Electrolyte Films

With the development of information society, the traditional von Neumann-based computing system is facing significant challenges. The search for an intelligent computing system similar to the biological brain would be a very effective solution to the present-day von Neumann bottleneck. Electrolyte-gated transistors (EGTs) have received much attention because they can simulate biological synaptic behavior very effectively. However, large-scale EGTs arrays are still lacking because most of the existing reported EGTs use organic or liquid electrolytes, which poses a significant challenge to the current production methods for manufacturing integration using photolithography. Although synaptic transistor arrays using solid-state electrolytes have the potential for large-scale fabrication, the power consumption required for individual transistors is relatively high. In this work, an electrolyte transistor array (10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 10) fabricated by the photolithography process was successfully proposed, where the individual transistors in the array used a composite polyvinyl alcohol (PVA)/lignin electrolyte as the gate dielectric layer. The switching ratio of a single transistor can reach 106, and the maximum gate leakage current is 43.96 pA in the voltage range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3 to 3 V. In addition, the synaptic properties, such as excitatory postsynaptic current (EPSC) and paired-pulse-facilitation (PPF), were successfully achieved. When the pulse duration is 100 ms, the energy consumption of the transistor is 0.63 nJ. The number’s dynamic memory and forgetting functions were also successfully simulated by the artificial synaptic transistor array. This work will provide a useful idea for large-scale array integration of EGTs using organic and liquid electrolytes as gate dielectric layers.

Ultrathin Crystalline Silicon Nano and Micro Membranes with High Areal Density for Low-Cost Flexible Electronics.

Ultrathin crystalline silicon is widely used as an active material for high-performance, flexible, and stretchable electronics, from simple passive and active components to complex integrated circuits, due to its excellent electrical and mechanical properties. However, in contrast to conventional silicon wafer-based devices, ultrathin crystalline silicon-based electronics require an expensive and rather complicated fabrication process. Although silicon-on-insulator (SOI) wafers are commonly used to obtain a single layer of crystalline silicon, they are costly and difficult to process. Therefore, as an alternative to SOI wafers-based thin layers, here, a simple transfer method is proposed for printing ultrathin multiple crystalline silicon sheets with thicknesses between 300nm to 13µm and high areal density (>90%) from a single mother wafer. Theoretically, the silicon nano/micro membrane can be generated until the mother wafer is completely consumed. In addition, the electronic applications of silicon membranes are successfully demonstrated through the fabrication of a flexible solar cell and flexible NMOS transistor arrays.

Carbon Nanotube Optoelectronic Synapse Transistor Arrays with Ultra‐Low Power Consumption for Stretchable Neuromorphic Vision Systems

AbstractHigh‐performance stretchable optoelectronic synaptic transistor arrays are key units for constructing and mimicking simulated neuromorphic vision systems. In this study, ultra‐low power consumption and low‐operation‐voltage stretchable all‐carbon optoelectronic synaptic thin film transistors (TFTs) using sorted semiconducting single‐walled carbon nanotubes (sc‐SWCNTs) modified with CdSe/ZnS quantum dots as active layers on ionic liquid‐based composite elastomer substrates are first reported. The resulting stretchable TFT devices show enhancement‐mode characteristics with excellent electrical properties (such as the record on/off ratios up to 105, negligible hysteresis, and small subthreshold swing), excellent mechanical tensile properties (such as the only 12.4% and 6.4% degradations of the carrier mobility after 20% vertical and horizontal strain stretching), and optoelectronic synaptic plasticity (for the recognition of Morse codes) with ultra‐low power consumptions (15.38 aJ) at the operating voltage from −1 to 0.2 V. At the same time, the designed nonvolatile conductance of the stretchable SWCNT optoelectronic synapse thin film transistors (SSOSTFTs) stimulated by UV light and the bending angle are first used to simulate stretchable neuromorphic vision systems (including the functions of the crystalline lens and optic cone cells as bionic eyes) for detecting the atmospheric environment with a record accuracy of 95.1% as a bionic eye.