Transient Enhanced Diffusion Of Dopants Research Articles

Improvement of the short channel effect in PMOSFETs using cold implantation

In this paper, to suppress transient enhanced dopant diffusion and improve short channel effects, cold implantation (cold-IIP) was applied to contact PLUG implantation in P-channel metal oxide semiconductor field effect transistors (PMOSFETs). A shallow dopant profile was formed by the suppression of transient enhanced diffusion (TED) due to the reduction of end-of-range (EOR) defects. Threshold voltage roll-off and off current (Ioff) increment, which are caused by a reduction in the distance between the gate and contact, were improved compared with room temperature implantation (RT-IIP). Additionally, the drain induced barrier lowering was improved, and the on-current improvement was attributed to reducing the contact resistance through the reduction of EOR defects. The contact resistance was reduced by ∼6% of the RT-IIP. In the DRAM device, the standby current at a short propagation delay time (tPD) was reduced effectively due to the decrease in the Ioff and contact resistance for the cold-IIP case.

A study of capping layers for sulfur monolayer doping on III-V junctions

Recently, high dosage doping on Si multi-gate field effect transistors and III–V planar structures using a self-limiting monolayer doping technique was reported to overcome challenges in scaling nano-sized transistors. The stoichiometry or composition of the capping layer was found to affect the diffusion efficiency of this process. In this work, we study the effect of a capping layer in sulfur monolayer doping on III–V junctions. Various capping temperatures and growth methods were compared. Based on the theoretical and experimental results, we suggest an optimized scheme consisting of a bi-layer capping structure. From Hall measurements and secondary ion mass spectrometry, a SiNx/BeO bi-layer capping, compared to single layer cap, exhibited the best results with a surface sheet resistance of 232 Ω/sq, junction depth of 11 nm, dopant profile abruptness of 3.5 nm/dec, electrically active S concentration of 4.9 × 1019/cm3 (=1.34 × 1013/cm2), and 3 times higher activation efficiency without significant transient-enhanced dopant diffusion.

Leakage current and defect characterization of p +n-source/drain diodes

A good control of the transient enhanced dopant diffusion is needed for MOSFET scaling down to the sub 50 nm regime. Carbon ion implant is known to significantly suppress the transient enhanced boron diffusion. However, carbon implantation is also reported to increase diode leakage current. This paper investigates the impact of ion implantation and annealing conditions during source/drain extension formation on leakage current behavior of boron/phosphorous diodes of PFET transistors. Analyzing the leakage current it is difficult to distinguish between the influence of the increased electric field due to the reduced diffusion and possible additional trap centers in the space charge region. This distinction can be made by electrical characterization, as shown in this paper. The leakage current mechanism is found to be trap assisted tunneling with phonon interaction. The corresponding trap energy within the band gap is 0.58 ± 0.10 eV. The carbon concentration in the space charge region measured by SIMS is below the detection limit. Also in electrical measurements, which are more sensitive, no significant influence of carbon related traps is observed. The leakage current is increased by the application of a Flash Anneal additionally to a Rapid Thermal Anneal for recrystallization of the silicon substrate.

Useful vacancies: Positron beam interrogation of fluorine-vacancy complexes in semiconductor device structures

The formation, migration and agglomeration in silicon of fluorine-vacancy complexes have been monitored by single-detector Doppler broadening spectroscopy. After electronics engineers found that fluorine ion implantation effectively eliminated the transient-enhanced diffusion of dopants in the creation of ultra-shallow junctions, a vital step in the further miniaturization of device structures, positron beams have played a pivotal role in providing an insight into the mechanisms underlying this phenomenon, being able to detect FV complexes in implanted and annealed samples. Secondary Ion Mass Spectrometry has provided complementary information on fluorine concentrations so that the nature of the F m V n complexes can be further assessed. New results on Si and SiGe structures are presented.

Effect of heating ramp rates on transient enhanced diffusion in ion-implanted silicon

Boron marker-layer structures have been used to analyze the heating ramp-rate dependence of transient enhanced dopant diffusion (TED) during rapid thermal annealing of Si implantation damage. The study uses short anneals with heating ramp rates in the range 0.1–350 °C/s, and peak temperatures in the range 900–1100 °C. Increasing the ramp rate is found to reduce the amount of profile broadening caused by TED, as well as reducing the smaller amount of normal “thermal-equilibrium” diffusion which is related to thermal budget. The results show why high ramp rates lead to improved B-implant activation and junction-depth control in Si devices. An Ostwald ripening model of interstitial-cluster evolution describes the detailed trends in the data and predicts further improvements in the case of ultrarapid annealing.

Dopant profile engineering of advanced Si MOSFET’s using ion implantation

Ion implantation has been used to realize non-uniform, steep retrograde (SR) dopant profiles in the active channel region of advanced Si MOSFET’s. After defining the transistor configuration, SR profiles were formed by dopant implantation through the polycrystalline Si gate and the gate oxide (through-the-gate, TG, implantation). The steep nature of the as-implanted profile was retained by applying rapid thermal annealing for dopant activation and implantation damage removal. For NMOS transistors, TG implantation of B yields improved transistor performance through increased carrier mobility, reduced junction capacitances, and reduced susceptibility to short-channel effects. Electrical measurements show that the gate oxide quality is not deteriorated by the ion-induced damage, demonstrating that transistor reliability is preserved. For PMOS transistors, TG implantation of P or As leads to unacceptable source/drain junction broadening as a result of transient enhanced dopant diffusion during thermal activation.

Formation, evolution and annihilation of interstitial clusters in ion implanted Si

Formation, thermal evolution and annealing kinetics of self-interstitial clusters in ion implanted Si have been investigated. Deep level transient spectroscopy measurements performed on epitaxial and Czochralski Si samples implanted with Si ions at energies of 145 keV or 1.2 MeV reveal that these clusters are formed for fluences above 10 12/cm 2 and annealing temperatures higher than 550°C. Interstitial clusters introduce seven well defined levels in the Si band gap at E V + 0.33 eV, E V + 0.52 eV, E C − 0.58 eV, E C − 0.50 eV, E C − 0.37 eV, E C − 0.29 eV and E C − 0.14 eV. Analysis of the annealing kinetics at temperatures in the range 550–700°C reveal that the clusters undergo Ostwald ripening and anneal out with a characteristic dissociation energy of ∼2.3 eV for a Si fluence of 1 × 10 12/cm 2. Furthermore, their annealing temperature increases with implantation fluence. These results indicate that small interstitial clusters act as the source of interstitial supersaturation that drive transient enhanced dopant diffusion in the absence of extended defects.

The Role of Trapped Interstitials During Rapid Thermal Annealing

ABSTRACTDuring the rapid thermal annealing of ion implanted layers, trapped interstitials are responsible for transient enhanced dopant diffusion and the formation of a band of defects at the mean projected ion range. We describe the detailed nature and extent of these effects and show how they can be predicted in practice. We present a model which explains why trapping only occurs with group V implantation and describe double implantation experiments which confirm the model and show how the formation of projected range defects can be suppressed.

Measurement of minority carrier lifetime in GaAs and [formula omitted] with an intensity-modulated electron beam : J. Pietzsch. Solid-St. Electron.25 (4), 295 (1982)

Ion implantation has been used to realize non-uniform, steep retrograde (SR) dopant profiles in the active channel region of advanced Si MOSFET’s. After defining the transistor configuration, SR profiles were formed by dopant implantation through the polycrystalline Si gate and the gate oxide (through-the-gate, TG, implantation). The steep nature of the as-implanted profile was retained by applying rapid thermal annealing for dopant activation and implantation damage removal. For NMOS transistors, TG implantation of B yields improved transistor performance through increased carrier mobility, reduced junction capacitances, and reduced susceptibility to short-channel effects. Electrical measurements show that the gate oxide quality is not deteriorated by the ion-induced damage, demonstrating that transistor reliability is preserved. For PMOS transistors, TG implantation of P or As leads to unacceptable source/drain junction broadening as a result of transient enhanced dopant diffusion during thermal activation.