Transient Effect Ring Oscillator Research Articles

A metastable RNG using interleaved NAND- and NOR-based TEROs

ABSTRACT This study introduces a novel approach to address the limitations observed in existing random number generator (RNG) designs, focusing on the resolution for insufficiently covered problem statements and study purposes. In response to these challenges, we propose a high-throughput metastable-based RNG tailored for cryptography applications. Our design is featured with a two-layer transient effect ring oscillator (TERO) architecture, meticulously crafted to mitigate the locking phenomenon and enhance RNG randomness. Leveraging interleaved two-layer TEROs, realised through NAND and NOR SR latches, our RNG achieves unpredictable irregular sampling, crucial for cryptographic applications. To further enhance irregular sampling, the first layer of the RNG employs a multiplexer that selects inputs randomly. This multiplexer is governed by selection signals generated by the second layer of the RNG, ensuring superior randomness. Implemented using TSMC 40-nm CMOS process, our RNG passed the FIPS 140–1 randomness test at a clock frequency of 100 MHz, boasting a remarkable throughput of 50 Mbps. This study represents a significant advancement in RNG technology, addressing previous shortcomings and paving the way for high-speed communication systems’ secure cryptographic applications.

Reliability analysis and comparison of ring-PUF based on probabilistic models

—To address the issue of maladaptive reliability theory models in delay-based physical unclonable functions (PUF) of ring classes, this paper begins by analyzing the relationship between four key transistor parameters (channel length, channel width, threshold voltage, and gate oxide thickness) and delay sensitivity. Then establishes reliability quantification formulas for various PUF types, including ring oscillator PUF, k-out-of-1 PUF, Loop PUF, transient effect ring oscillator PUF, and duty cycle PUF. This analysis and comparison are conducted using the inverter delay model and probabilistic statistical methods to ensure fairness at the theoretical level. Finally, the proposed model is validated through simulation experiments, along with further analysis and comparison of ring-PUF. The results demonstrate that delay sensitivity can be utilized to assess the extent of delay impact when process parameters fluctuate. In terms of reliability, the ring-PUF can be ranked as follows: k-out-of-1 PUF, Loop PUF, ring oscillator PUF, transient effect ring oscillator PUF, and duty cycle PUF. This paper offers extensive technical guidance and theoretical support for ring PUF designers.

Entaglement and communication in digital qubits using FPGAs

Abstract This paper focuses on usage of digital qubits on a digital quantum computing platform implemented on FPGAs. Modifications have been made to existing digital qubit standards to account for complex probability amplitudes and not only real ones. This paper introduces an improved transient effect ring-oscillator based TRNG used in the scope of this project. The objective of this was to simulate the addition of environmental noise in a digital setting. Using the newly designed digital qubits, a few quantum logic gates have been designed to work on the FPGA platform using Verilog. These logic gates have then been used to implement entanglement on a digital hardware platform. Furthermore, this paper implements communication between two digital quantum computers over both wired and wireless media by transmitting alphabetical messages as qubits and compares the same with transmission involving classical digital bits only.

Design and analysis of DDoS mitigating network architecture.

Distributed Denial of Service (DDoS) attacks have emerged as the top security threat with the rise of e-commerce in recent years. Volumetric attacks are the most common DDoS attacks that aim to overwhelm the victim's bandwidth. The current mitigation methods use reactive filtering techniques that are not magical and straightforward solutions. In this paper, we propose a network architecture based on the capability to address the threat of DDoS attacks. Physically Unclonable Functions (PUFs) have emerged as a promising solution in security. Motivated by the capability approach, we put forward a network architecture where the routers use Transient Effect Ring Oscillator PUF to generate and verify capabilities. This novel hardware-based solution, to address the problem, has reduced the computational overhead of capability generation. Additionally, the destination has complete control over the incoming traffic in the proposed architecture, resulting in uninterrupted communication with the legitimate clients regardless of the attacker traffic. The large-scale simulation on an open-source Network Simulator (NS-3) has shown that the proposed architecture efficiently mitigates DDoS attacks to a large extend. With our proposed architecture, the throughput was hardly affected when attacker traffic was varied from 10 to 80%.

A Reconfigurable Random Number Generator Based on the Transient Effects of Ring Oscillators

This brief presents a reconfigurable Random Number Generator (RNG) based on transient effect of ring oscillators. Users can select a method based on the irregular sampling of a regular waveform or on the regular sampling of an irregular waveform to obtain a random bit sequence to be used in different applications, such as lightweight cryptography or high-security communication. The entropy is acquired by exploiting Transient Effect Ring Oscillators (TEROs). The proposed fully-digital RNG structure is firstly implemented on a Zynq-7000 FPGA (Field Programmable Gate Array) without any post-processing method such as the Von Neumann. In addition to the RNG structure, an on-the-line test module based on FIPS 140–2 is also implemented to check the randomness of the produced data statistically in real time. Users can change the statistical test parameters according to their desired security levels. Finally, an ASIC (Application Specific Integrated Circuits) implementation of the proposed RNG is done following the Cadence digital design flow for the TSMC 180 nm CMOS process. The implemented ASIC design occupies an area of 0.85 mm x 0.85 mm and the estimated power required is 11.827 mW.

Experimental Study of Locking Phenomena on Oscillating Rings Implemented in Logic Devices

Oscillating rings are widely used in CMOS logic devices because they are easy to integrate, require low area and low power. Their main disadvantage is that they tend to lock to each other and/or to an external periodic signal. This locking phenomenon can render a system based on a freely running oscillator non-functional. A detailed study of the causes of the phenomenon and how to avoid it, is therefore of paramount importance. In this paper, we conduct a detailed examination of the locking phenomenon using the most commonly used rings: ring oscillators, transient effect ring oscillators, and self-timed rings. We then analyze the consequences of locking on different use cases based on oscillating rings and provide design recommendations to minimize its impact. Our results could help designers better anticipate locking phenomenon in their future designs. To ensure reproducibility of the results, the VHDL code of all the experiments is available and can be downloaded from a dedicated web page.

Improving performance of FPGA-based SR-latch PUF using Transient Effect Ring Oscillator and programmable delay lines

In this paper, we propose a new structure of SR-Latch Physically Unclonable Function (PUF) based on Transient Effect Ring Oscillator (TERO). Our proposed TERO-based scheme combines the features of two different programmable delay lines (PDLs) and generates the response bits by comparing the number of oscillations of the SR-Latches during the metastable state. The proposed scheme reduces the impact of environmental noise to increase the reliability of the response bits. Also, our proposed area-efficient PUF architecture has low complexities and hence consumes low power consumption as compared to the counterparts. Moreover, we investigate the impact of systematic variation on the uniqueness of the response bits. We have used an optimized placement (in term of area cost) for the proposed structure and implemented our proposed scheme on the Spartan3 FPGA boards. The implemented structure demonstrates considerable performance metrics such as the uniqueness of 49.32%. In addition, the proposed structure provides higher reliability when tuned with PDLs. Hence, the need for complex error correcting codes is reduced. This makes the scheme appropriate for low-cost authentication and cryptographic applications.

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF

Today, life is becoming increasingly connected. From TVs to smartphones, including vehicles, buildings, and household appliances, everything is interconnected in what we call the “Internet of Things” (IoT). IoT is now part of our life and we have to deal with it. More than ten billion devices are already connected and five times more are expected to be deployed in the next five years. While deployment and integration of IoT is expanding, one of the main challenge is to provide practical solutions to security, privacy, and trust issues in IoT. Protection and security mechanisms need to include features such as interoperability and scalability but also traceability, authentication, and access control while remaining lightweight. Among the most promising approaches to such security mechanisms, physical unclonable functions (PUFs) provide a unique identifier for similar but different integrated circuits using some of their physical characteristics. These types of functions can thus be used to authenticate integrated circuits, provide traceability and access control. This paper presents a comprehensive case study of the transient effect ring oscillator (RO) PUF from its implementation on FPGAs to its complete characterization. The implementation of the PUF is detailed for two different families of FPGAs: 1) Xilinx Spartan 6 and 2) Altera Cyclone V. All the metrics used for the characterization are explained in detail and the results of the characterization include robustness to environmental parameters including variations in temperature and voltage. Finally, we compare our results with those obtained for another PUF: the RO PUF. All the design files are available online to ensure repeatability and enable comparison of our contribution with other studies.

Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators

This paper proposes a theoretical study and a full overview of the design, evaluation, and optimization of a PUF based on transient element ring oscillators (TERO-PUF). We show how, by following some simple design rules and strategies, designers can build and optimize a TERO-PUF with the state-of-the-art PUF characteristics in a standard CMOS technology. To this end, we analyzed the uniqueness, steadiness, and randomness of responses generated from 30 test chips in a CMOS 350-nm process in nominal and corner voltage and temperature conditions. Response generation schemes are proposed and discussed to optimize the PUF performances and reduce its area without noticeable loss in its output quality. In particular, we show that the large area of the basic blocks in the TERO-PUF is balanced by the high level of entropy extracted in each basic block. Guidelines are provided to balance reliability and randomness of the responses and the design area.

A PUF Based on a Transient Effect Ring Oscillator and Insensitive to Locking Phenomenon

This paper presents a new silicon physical unclonable function (PUF) based on a transient effect ring oscillator (TERO). The proposed PUF has state of the art PUF characteristics with a good ratio of PUF response variability to response length. Unlike RO-PUF, it is not sensitive to the locking phenomenon, which challenges the use of ring oscillators for the design of both PUF and TRNG. The novel architecture using differential structures guarantees high stability of the TERO-PUF. The area of the TERO-PUF is relatively high, but is still comparable with other PUF designs. However, since the same piece of hardware can be used for both PUF and random number generation, the proposed principle offers an interesting low area mixed solution.