Transient Circuit Research Articles

Fast transient response high‐accuracy current‐sensing technique for step‐up DC–DC converter

A novel current-sensing technique with fast transient and high accuracy for a step-up DC–DC converter is presented. This circuitry is applied for sensing the current flowing through the equivalent series resistor (ESR) of the inductor to obtain the inductor current information. It is achieved with a fast transient response circuit (FTRC), an operational amplifier, a current-sensing stage and an overshoot current protection circuit. The process offsets of the transistors, which can increase the current-sensing accuracy, and provide an additional current feedback loop to decrease the transient response time are compensated by the FTRC. When the sensed current is higher than the maximum value, the overcurrent protection (OCP) will be operating to let it shut down. This current-sensing technique has been integrated in a step-up DC–DC converter with standard 0.35 μm CMOS process. Experimental results show that the accuracy is higher than 98% and the transient response recovery time is ∼100 μs with load current changing from 3 A to 10 mA.

Dead-Beat Current Controller for Voltage Source Converters with Improved Large Signal Response

A digital dead-beat current controller for voltage source converters is presented in this paper. The control structure is specified in a digital hardware description language, synthesized, and deployed on a field-programmable gate array chip. By updating, with negligible computation delay, the duty cycle twice in a switching period, the reference current error is nulled in half a modulation period, so that the controller's small-signal bandwidth is maximized. In addition, due to a simple transient detection circuit, the large-signal response delay is reduced to a small fraction of the modulation period, which is determined by the chosen current signal oversampling rate. The controller can effectively support different voltage-source inverter applications, such as active filters, uninterruptible power supplies, microgrid distributed energy resource controllers, and dc–dc converter applications, including interface converters for renewable energy sources, laboratory battery chargers, and electronic welding machines.

Energy-Efficiency and Accuracy of Stochastic Computing Circuits in Emerging Technologies

The continued scaling of feature sizes in integrated circuit technology leads to more uncertainty and unreliability in circuit behavior. Maintaining the paradigm of deterministic Boolean computing therefore becomes increasingly challenging. Stochastic computing (SC) processes digital data in the form of long pseudo-random bit-streams denoting probabilities and is therefore less vulnerable to uncertainty. When transient circuit variations are present, SC greatly outperforms classical binary implementations. Under these circumstances, it is impossible for binary systems to achieve arbitrarily low error rates, while SC can still trade-off precision for energy by using longer bit-streams. This makes the technique a valuable alternative to binary logic in emerging technologies with high inherent transient uncertainty. This paper assesses the feasibility of multi-stage SC and discusses energy and accuracy considerations in SC design. First, the basics of SC-circuit design are discussed. Second, we investigate three different sources of noise or uncertainty and assess their impact on SC accuracy. Third, we propose a methodological design strategy to evaluate the accuracy of general, multi-stage SC systems. The validity of this new approach is illustrated through the design of a 1D-DCT stochastic circuit, as part of a JPEG compression accelerator. Our analysis shows multi-stage stochastic computing requires very long word lengths to achieve high accuracy, resulting in low energy efficiency. Exploiting stochastic computing's transient error tolerance in emerging technologies will thus have a high energy cost.

Recapillarity: Electrochemically Controlled Capillary Withdrawal of a Liquid Metal Alloy from Microchannels

This paper describes the mechanistic details of an electrochemical method to control the withdrawal of a liquid metal alloy, eutectic gallium indium (EGaIn), from microfluidic channels. EGaIn is one of several alloys of gallium that are liquid at room temperature and form a thin (nm scale) surface oxide that stabilizes the shape of the metal in microchannels. Applying a reductive potential to the metal removes the oxide in the presence of electrolyte and induces capillary behavior; we call this behavior “recapillarity” because of the importance of electrochemical reduction to the process. Recapillarity can repeatably toggle on and off capillary behavior by applying voltage, which is useful for controlling the withdrawal of metal from microchannels. This paper explores the mechanism of withdrawal and identifies the applied current as the key factor dictating the withdrawal velocity. Experimental observations suggest that this current may be necessary to reduce the oxide on the leading interface of the metal as well as the oxide sandwiched between the wall of the microchannel and the bulk liquid metal. The ability to control the shape and position of a metal using an applied voltage may prove useful for shape reconfigurable electronics, optics, transient circuits, and microfluidic components.

Analytic computation for steady states of loaded self-excited induction generators

Based on the state-space mathematic model obtained from the transient equivalent circuits in two-phase stationary reference frame of the loaded self-excited induction generator, a holistic analysis approach using Lyapunov stability theory was proposed for the whole of transient and steady state process of self-excitation buildup. According to the approach, it was obtained the steady-state conditions for self-excitation buildup represented by the transient mathematic model. The limit cycle condition was solved to get analytic formulas of the stator frequency and rotor speed, as well as the load ranges and analytic relationship of the magnetizing inductance for self-excitation buildup. In order to solve the steady-state operating point condition, an equivalent transformation method based on the physical occasion was presented to analytically compute all the points. The example analysis tested and confirmed only a set of analytic formulas. Good agreement between measured and computed results verified correctness, scientificalness and high validity of the steady-state conditions analytic formulas, showing universality and referenced value in engineering. It was solved the problem of the transient and steady state operating performance of induction generators unable to be analytically computed for a long time. The approach could be applicable to performance analysis of other power systems of dynamics.

Large Current GaAs PCSS Triggered by a Laser Diode

We have fabricated a 2-mm gap semi-insulating GaAs photoconductive semiconductor switch (PCSS), and obtained a 1.45-kA large current under a bias voltage of 6 kV when the PCSS was triggered by a 4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(\mu \) </tex-math></inline-formula> J commercial laser diode. An RLC transient circuit model was employed to get the electrical properties of the PCSS in the transient discharge process. The reason for the switch exiting from nonlinear operating mode was that the electric field across the switch dropped below the lock-on field. This letter shows the attractive prospect of a low-cost compact high-power pulse source with the GaAs PCSS.

A 10 GW Tesla-Driven Blumlein Pulsed Power Generator

A repetitive 0.6 MV, 10 GW Tesla-driven Blumlein pulsed power generator, with an overall energy efficiency in excess of 90%, has been designed, manufactured and demonstrated by the Pulsed Power Group at Loughborough University. This paper describes the application of various numerical techniques used to design a successful generator, such as filamentary modeling and electrostatic and transient circuit analysis. All the major parameters of both the Tesla transformer and the Blumlein pulse-forming line were determined, enabling accurate modeling of the overall unit to be performed. The wide-bandwidth embedded sensors used to monitor the dynamic characteristics of the overall system are also presented. Experimental results obtained during this major experimental program are compared with theoretical predictions and the way ahead toward generating faster output voltage impulses is considered.

A Nine-Level Grid-Connected Converter Topology for Single-Phase Transformerless PV Systems

This paper presents a single-phase transformerless grid-connected photovoltaic converter based on two cascaded full bridges with different dc-link voltages. The converter can synthesize up to nine voltage levels with a single dc bus, since one of the full bridges is supplied by a flying capacitor. The multilevel output reduces harmonic distortion and electromagnetic interference. A suitable switching strategy is employed to regulate the flying-capacitor voltage, improve the efficiency (most devices switch at the grid frequency), and minimize the common-mode leakage current with the help of a novel dedicated circuit (transient circuit). Simulations and experiments confirm the feasibility and good performance of the proposed converter.

Low quiescent current linear regulator using combination structure of bandgap and error amplifier

A low quiescent current low dropout linear regulator (LDR) with a combination structure of a bandgap and an error amplifier is presented. The circuitry is achieved with a combined structure which is able to obtain a lower quiescent current, because the current for the specific bandgap reference can be omitted. The transient response enhancement circuit can activate an additional path to control the gate voltage of the pass device which assists in monitoring the variation in the output voltage in the steady state. According to restrictions of the process and the product requirements, this proposed LDR is implemented with high-voltage tolerance double-diffused MOS (DMOS) in a 0.6 μm BCD process. The LDR has a quiescent current of 3 μA and is able to deliver a 50 mA load current.

Memristor: Part II–DC, Transient, and RF Analysis

The dc and RF circuit performance of memristor circuits, including transient behavior, is developed by considering current contributions arising from different conduction mechanisms, namely, filament-assisted and bulk tunneling currents and currents flowing through low and high conductivity filaments. The dc circuit model explains the observed I-V hysteresis and most importantly allows scaling and optimization. A transient circuit model of memristive system is developed, based upon the dynamics, incorporating underlying electrochemistry that suggests SET and RESET transitions for a 50-nm TiO2-based memristor take approximately 120 ps to stabilize. A faster READ/WRITE operation would require appropriate conditioning circuitry. RF analysis suggests for a maximum allowable frequency of 7.5 GHz beyond which memristors can no longer be used as RRAM. These values can be pushed to higher limits by increasing the device cross-sectional area or choosing lower permittivity materials. The developed model allows its incorporation in commercial circuit simulators. The derived model is validated by incorporating it in Chua's chaotic circuit.

A transient enhanced DVS DC–DC converter based on state trajectory analysis

Dynamic voltage scaling (DVS) can effectively reduce energy consumption by dynamically varying the supply voltage of the system accordingly to the clock frequency. A new DVS-enabled DC–DC converter is presented in this paper. State trajectory is employed to analyze the transient features of PWM and PFM Buck converters. A novel transient enhancement circuit is designed to improve the transient response of the DVS-enabled Buck converter. To further expand the output voltage range of the converter, a current-starved voltage controlled delay line is proposed in the controller of DC–DC converter to obtain an ultra low voltage of 0.5 V. When the input voltage is 3.3 V, the output voltage of the converter can be dynamically regulated from 0.5 to 2.0 V. The output voltage tracking speed is less than 7.5 μs/V and the recovery speed is 33 μs/A for a load current step from 0.6 to 0.2 A at output voltage of 0.5 V. The chip area is 1.75 mm × 1.33 mm in a 0.18 μm standard CMOS process.

Subharmonic Oscillations Induced by Continuous Wave Electromagnetic Interference on a Microwave Phase-Locked Loop

This paper presents measurements, simulations, and a theoretical basis to support the observation of spurious peaks on the output spectrum of a microwave phase-locked loop (PLL) exposed to a continuous wave electromagnetic interference (EMI). It is shown that high-power EMI combined to nonlinear characteristics of the PLL may induce subharmonic oscillation phenomena, which provoke the appearance of spurious peaks on the output spectrum. Measurements show that in addition to their dependence on the EMI power and frequency, these spurious peaks depend also on the natural frequency of the PLL and on its stability. Transient circuit simulations of the PLL allowing the prediction of these spurious peaks are presented. Finally, a theoretical explanation based on an analysis of a second-order PLL is given.

Chapter Three - Malformations of Cortical Development and Neocortical Focus

Developmental neocortical malformations resulting from abnormal neurogenesis, disturbances in programmed cell death, or neuronal migration disorders may cause a long-term hyperexcitability. Early generated Cajal-Retzius and subplate neurons play important roles in transient cortical circuits, and structural/functional disorders in early cortical development may induce persistent network disturbances and epileptic disorders. In particular, depolarizing GABAergic responses are important for the regulation of neurodevelopmental events, like neurogenesis or migration, while pathophysiological alterations in chloride homeostasis may cause epileptic activity. Although modern imaging techniques may provide an estimate of the structural lesion, the site and extent of the cortical malformation may not correlate with the epileptogenic zone. The neocortical focus may be surrounded by widespread molecular, structural, and functional disturbances, which are difficult to recognize with imaging technologies. However, modern imaging and electrophysiological techniques enable focused hypotheses of the neocortical epileptogenic zone, thus allowing more specific epilepsy surgery. Focal cortical malformation can be successfully removed with minimal rim, close to or even within eloquent cortex with a promising risk-benefit ratio.

Performance Evaluation of 14 nm FinFET‐Based 6T SRAM Cell Functionality for DC and Transient Circuit Analysis

As the technology node size decreases, the number of static random‐access memory (SRAM) cells on a single word line increases. The coupling capacitance will increase with the increase of the load of word line, which reduces the performance of SRAM, more obvious in the SRAM signal delay and the SRAM power usage. The main purpose of this study is to investigate the stability and evaluate the power consumption of a 14 nm gate length FinFET‐based 6T SRAM cell functionality for direct current (DC) and transient circuit analysis, namely, in resistor‐capacitor (RC) delay. In particular, Berkeley Short‐channel IGFET Model‐Common Multigate (BSIM‐CMG) model is utilized. The simulation of the SRAM model is carried out in HSPICE based on 14 nm process technology. A shorted‐gate (SG) mode FinFET is modeled on a silicon on insulator (SOI) substrate. It is tested in terms of functionality and stability. Then, a functional SRAM is simulated with 5 GHz square wave at the input of word line (WL). Ideal square wave and square wave with 100 RC, 5 RC, 1 RC, and 0.5 RC are asserted to the WL and the bit lines (BL&amp;BLB) of SRAM. Voltage at node q and is observed. The simulation shows that 1 RC is the minimum square wave that will store correct value in node q and node . Thus, this discovery from the research can be used as a modeling platform for circuit designers to explore and improve the SRAM tolerance against RC delay.

Simulation technique for ACLR of a class‐S power amplifier with a delta‐sigma modulator

ABSTRACTA simulation technique for an adjacent channel leakage ratio (ACLR) of a class‐S power amplifier (PA) with a delta‐sigma modulator is proposed. This technique is based on three basic points. The first is a proper baseband signal, which must provide a fairly better ACLR than the target value of a PA as well as a tolerable total amount of time that can be handled by a transient circuit simulation. The second point is a carrier frequency adjustment for the observations free from spectrum leakage distortion due to a limited total amount of simulated time. The last is an ACLR calculation using only a steady‐state output. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:462–465, 2014

Negative voltage surge resistant circuit design in HVIC

A reliable and methodical solution to restrain transient undershoot on VS pin for a high-voltage gate drive circuit with a transient negative voltage detector circuit (TNVDC) is proposed. The proposed TNVDC circuit does not consume any quiescent current while the chip works normally and it is totally integrated in a high-voltage integrated circuit (HVIC) without any additional discrete devices in the system. The proposed circuit could send a control signal to the drive stage of the HVIC for decreasing the sink current while the transient undershoot of the VS is excessive. The measurement shows that the negative voltage surge tolerance is −98 V of the HVIC with TNVDC.

Determining Minimum Printed Circuit Board Trace Dimensions for Transient Suppression Circuits

When designing transient suppression circuits housed on interface assemblies to protect internal circuits from power surges, there exists a need to accurately determine the minimum printed circuit board (PCB) trace width required to tolerate given transients without fusing due to overheating. This paper presents four different PCB trace models that may be used for this purpose. The predicted trace widths are compared with each other for validation by comparison. In addition, selected results are tested to further validate the accuracy of the models.

A compact model for tunnel field-effect transistors incorporating nonlocal band-to-band tunneling

To enable circuit design using tunnel field-effect transistors (TFETs), a physics-based model based on nonlocal band-to-band tunneling is developed. To maintain accuracy, the tunneling lengths are estimated assuming that both vertical and horizontal tunneling paths exist in the device. The static current-voltage characteristics are modeled, including the diode currents and Esaki tunneling. Parasitic capacitances and resistances are included to enable transient circuit analyses. The model is validated by comparison with measurements of silicon TFETs, as well as with semiconductor device simulations based on nonlocal band-to-band tunneling. The model accounts for TFET behavior in circuits, as demonstrated by simulations of inverters and static random access memories. Consequently, the model can be used to develop TFET circuits for low-power applications.

Rotors during AF: drivers or bystanders?

This editorial refers to ‘Epicardial wave mapping in human long-lasting persistent atrial fibrillation: transient rotational circuits, complex wavefronts, and disorganized activity’, by G. Lee et al. doi:10.1093/eurheartj/eht267 In the study of Lee and co-workers,1 in 18 patients undergoing open heart surgery for mitral or aortic valve disease, high-density mapping of the atria was performed (128 electrodes/6.75 cm2). The mapping plaque was positioned consecutively on the left and right atrial appendages, the posterior wall of the left atrium, and the right superior pulmonary vein (RSPV)–left atrial (LA) junction. In the majority of maps, activation patterns were highly heterogeneous, with multiple unstable activation patterns transitioning from one to another during each recording. The most common patterns seen were multiple wavefronts (56.2 ± 32%) and disorganized activity (24.2 ± 30.3%). Focal activations accounted for 11.3 ± 14.2% of activations and were all short lived ( ≤2 beats), with no site demonstrating sustained focal activity. Two of 36 maps (5.5%) showed a stable activation pattern, consisting of consecutive planar wavefronts propagating in the same direction. Only three transient rotational circuits were observed [two in the posterior left atrium and one on the anterior surface of the left atrial appendage (LAA)]. Two of these circuits lasted for only 5–7 revolutions, whereas the third broke up within < 5 s. On the basis of these observations, the authors conclude that: ‘Human long-lasting persistent AF is characterized by heterogeneous and unstable patterns of activation including multiple wavefronts, transient rotational circuits, and disorganized activity’. The investigators have to be complimented on their efforts carefully to visualize and dissect the complex activation patterns during long-standing human atrial fibrillation (AF). Studies like these are quite scarce, because attempts to diagnose the underlying substrate of AF are very time-consuming and usually considered less attractive than evaluating the rate of …

Multi-GHz Synchronous Waveform Acquisition With Real-Time Pattern-Matching Trigger Generation

A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 μm CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High-above the high threshold, Low-below the low threshold, Middle-between the two thresholds, or “Don't Care”-any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has been measured to be about 1 part per million, RMS.