Transfer Torque Random Access Memory Research Articles

EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit

Spin Transfer Torque Random Access Memory (STT-RAM) has garnered interest due to its various characteristics such as non-volatility, low leakage power, high density. Its magnetic properties have a vital role in STT switching operations through thermal effectiveness. A key challenge for STT-RAM in industrial adaption is the high write energy and latency. In this paper, we overcome this challenge by exploiting the stochastic switching of STT-RAM cells and, in tandem, with circuit-level approximation. We enforce the robustness of our technique by analyzing the vulnerability of write operation against radiation-induced soft errors and applying a low-cost improvement. Due to serious reliability challenges in nanometer-scale technology, the robustness of the proposed circuit is also analyzed in the presence of CMOS and magnetic tunnel junction (MTJ) process variation. Compared to the state-of-the-art, we achieve 33.04% and 5.47% lower STT-RAM write energy and latency, respectively, with a 3.7% area overhead, for memory-centric applications.

Optoelectronic Readout of STT-RAM Based on Plasmon Drag Effect

An opto-electronic readout of the memory state in spin transfer torque random access memory (STT-RAM) cells is proposed. A single optical beam illuminating an array of STT-RAM cells creates electrical potential along each STT-RAM cell due to optical rectification that can be further enhanced through plasmon drag effect (PLDE). Then, the photo-induced voltage is assumed to be measured by conventional electronics. Here, a theoretical modeling is performed, where the results provide an estimate of the photo-induced voltage in each memory cell and its variation with respect to the changes in state of the memory cell (parallel vs anti-parallel). Our study shows that the plasmonic enhancement facilitates ${\sim }$ 20 times enhancement in the voltage change due to state change of the each memory cell, compared to the case of out-of-resonance excitation. This enhancement potentially improves the memory readout rate if a proper supporting electronic circuit is available.

Design and optimize giant spin-Hall effect spin transfer torque random access memory using optical switching connections

Design and optimize giant spin-Hall effect spin transfer torque random access memory using optical switching connections

Computational investigation of half-Heusler/MgO magnetic tunnel junctions with (001) orientation

A series of half-metallic XYZ half-Heusler alloys is combined with MgO to create Heusler–MgO junctions. The electronic and magnetic properties of these junctions are investigated. The strong oxidation between metal and oxygen atoms causes the systems with pure YY interfaces to be the most stable cases. We conclude that uniaxial anisotropy can be induced in Heusler layers adjacent to MgO. The type of interface layers determines the half-metallicity and anisotropy (in-plane or perpendicular) in the Heusler–MgO junctions. The capacity to retain both half-metallicity and perpendicular magnetic anisotropy in NiMnSb/MgO and CoTiSn/MgO junctions with a MnMn interface layer makes these structures potential candidates as electrode layers in spin transfer torque random access memory devices.

Study on Energy Reduction Techniques in STT-RAM

Spin Transfer Torque Random Access Memory (STT-RAM) is suitable to be considered for cosmic memory. In STT-RAM the altercative period of attractive burrowing intersection is exchanged by the showing up of turn enraptured current over the intersection and it appear to be the most preparing elective with the more thickness and low introduction power, one of the major test for STT-RAM is the more write current, this paper proposes dual source write assist circuit method to reduce the equal compose vitality that prompts a diminishing in power utilization and the limit voltage of dynamic transistor to rising temperature. The MTJ temperature will increase than the write error rate is reduced. The final result is by effective use of VDD and threshold voltage values the write energy will be reduced. Right now, results utilizing a CMOS 65-nm get to transistor and the 40-nm MTJ innovation affirm that the projected compose help strategy prompts 81% of robustness is spared and its further incorporates just 9.6% territory excess to a 16-kb of STT-RAM cluster. And furthermore, another compose help technique is proposed to the end the compose activity in the wake of exchanging happens in the attractive burrowing intersection (MTJ), thus the both compose time vitality utilization of 1T-1MTJ piece cells will create.

Array of symmetric nanohole dimers with high sensitivity for detection of changes in an STT-RAM ultrathin dielectric layer

A dimer nanohole array is proposed for in situ characterization of radiation damages in spin transfer torque random access memory (STT-RAM) multilayer structures. The structure supports a Fano resonance, which is about twice as sensitive to the refractive index changes in the surface layer, compared to the plasmonic mode in single nanohole arrays. A simplified STT-RAM multilayer of air/gold(5 nm)/MgO(10 nm)/gold(60 nm)/quartz substrate is considered as the platform for the dimer nanohole array. Our studies show that regarding the changes in the ultrathin MgO layer, the normalized figure of merit for this structure is up to more than 10 times larger than an array of single nanoholes. Furthermore, an improvement in bulk sensing performance over the array of nanohole heptamers is observed.

Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

PurposeThe purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM).Design/methodology/approachSpintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ.FindingsIt is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit.Originality/valueThis paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

Write‐variation aware alternatives to replace SRAM buffers with non‐volatile buffers in on‐chip interconnects

With the advancement in CMOS technology and multiple processors on the chip, communication across these cores is managed by a network-on-chip (NoC). Power and performance of these NoC interconnects have become a significant factor.The authors aim to reduce the leakage power consumption of NoC buffers by the use of non-volatile spin transfer torque random access memory (STT-RAM)-based buffers. STT-RAM technology has the advantages of high density and low leakage but suffers from low endurance. This low endurance has an impact on the lifetime of the router on the whole due to unwanted write-variations governed by virtual channel (VC) allocation policies. Here various VC allocation policies that help the uniform distribution of the writes across the buffers are proposed. Iso-capacity and iso-area-based alternatives to replace SRAM buffers with STT-RAM buffers are also presented. Pure STT-RAM buffers, however, impact the network latency. To mitigate this, a hybrid variant of the proposed policies which uses alternative VCs made of SRAM technology in the case of heavy network traffic is proposed. Experimental evaluation of full system simulation shows that proposed policies reduce the write variation by 99% and improve lifetime by 3.2 times and 1093 times, respectively. Also a 55.5% gain in the energy delay product is obtained.

Temperature dependence of magnetic properties on switching energy in magnetic tunnel junction devices with tilted magnetization

Spin transfer torque random access memory (STT-RAM) based on magnetic tunnel junction (MTJ) is a popular type of memory because of its non-volatility, small size, and nanosecond access time. The temperature effect on the magnetic properties and the initial angle between the free and pinned layer magnetizations in the MTJ cell are significant for the fast switching process in STT-RAM. In this study, the switching energy was investigated with the temperature effect on the magnetic properties at various initial angles. The results show that the saturation magnetization was decreased by increments of the initial temperature, which also resulted in the reduction of the intrinsic critical current density. Consequently, switching energy can be reduced by the increase of both the initial temperature and the initial angle. Although the initial temperature increment in the MTJ cell is interesting for the fast switching process in STT-RAM, the thermal stability factor greater than 40 and the Curie temperature were both considered for the analysis of the switching energy with magnetic properties, for stabilizing the operation of STT-RAM.

Perpendicular magnetic anisotropy in Mn2VIn (001) films: An ab initio study

First principles study of the magnetic anisotropy of Mn2VIn (001) films show perpendicular magnetic anisotropy (PMA), which increases as a function of the thickness of the film. Density functional theory (DFT) as implemented in the Vienna Ab initio simulation package (VASP) is employed here to perform a comprehensive theoretical investigation of the structural, electronic and magnetic properties of the Mn2VIn(001) films of varying thickness. Our calculations were performed on fully relaxed structures, with five to seventeen mono layers (ML). The degree of spin polarization is higher in the (001) Mn2VIn thin films as compared to the bulk in contrast to what is usually the case and as in Mn2VAl, which is isoelectronic to Mn2VIn as well as inCo2VIn (001) films studied for comparison. Tetragonal distortions are found in all the systems after relaxation. The distortion in the Mn2VIn system persists even for the 17ML thin film, resulting in PMA in the Mn2VIn system. This significant finding has potential to contribute to spin transfer torque (STT) and magnetic random access memory MRAM applications, as materials with PMA derived from volume magnetocrystalline anisotropy are being proposed as ideal magnetic electrodes.

Micro‐architectural approach to the efficient employment of STTRAM cells in a microprocessor register file

In this paper, the authors propose two approaches that employ spin transfer torque random access memory (STTRAM) in the design of the register file, an important part of embedded processors. However, STTRAM suffers from both endurance and latency in the write operation. Consequently, employing STTRAM in the register file entails two challenges: (i) the lifetime significantly decreases as data are frequently written into a register file; (ii) the delay of the critical path increases as a result of the slow write operation. They have proposed using two well-known micro-architectural approaches: the last-write-update (LWU) and the value locality (VL), to minimize the number of write operations into a register. The main observation behind LWU is that only the last write operations of certain registers in the re-order buffer should be considered. VL exploits the fact that a limited number of values are more likely to be written into a register file. Their simulation shows that by employing the LWU and VL approaches, the lifetime of the STTRAM-based register file, compared with the lifetime of traditional static RAM-based register file architecture, extends to about 40 years on average and around 3.5 years in the worst case while improving power consumption by 30%.

Angular Dependence of Spin Transfer Switching in Spin Valve Nanopillar Based Heusler Alloy

The spin transfer induced magnetization switching in current perpendicular-to-the-plane spin valve nanopillar based Co2FeAl0.5Si0.5Heusler alloy with varying the initial angles of the magnetization of sensing layer,θ0, was investigated via macrospin simulations. The effects of an in-plane magnetic field,Hi, on the switching behavior were also evaluated. The magnetization switching was excited by spin polarized switching current,Is. The time varying magnetization was computed by the Landau-Lifshitz-Gilbert-Slonczewski equation, while the spin transfer induced noise was examined by using the power spectral density analysis. It was found thatθ0should be narrowly initialized since this configuration produces the small noise during the switching. Also, the negativeIsproduced more uniform switching than the positiveIsdue to existence of ferromagnetic exchange coupling. WhenHiwas presented, the noise generated at low frequencies could be suppressed, and then the switching behavior became more uniform. In addition, the results indicated that the noise configuration could be explained by the physical dynamic of magnetization behavior. Hence, the spin transfer induced noise needs to be minimized in order to improve the performance of spin transfer torque random access memory for high density recording.

Performance analysis of STT-RAM with cross shaped free layer using Heusler alloys

We have investigated the performance of a spin transfer torque random access memory (STT-RAM) cell with a cross shaped Heusler compound based free layer using micromagnetic simulations. We have designed a free layer using a Cobalt based Heusler compound. Simulation results clearly show that the switching time from one state to the other state has been reduced, also it has been found that the critical switching current density (to switch the magnetization of the free layer of the STT RAM cell) is reduced.

A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory

Resistive nonvolatile memory (NVM) devices such as spin transfer torque random access memory (STT-RAM) and resistive random access memory are considered to be leading candidates for next-generation memory devices. With technology scaling, the sensing margin (SM) of the resistive NVM devices is significantly degraded because of increased process variation and decreased read current. In this brief, we propose an offset-canceling dual-stage sensing circuit (OCDS-SC) that has the two major advantages of offset voltage cancelation and double SM. Monte Carlo HSPICE simulation results using a 45-nm technology for STT-RAM show that the OCDS-SC achieves a read access yield of 99.93% for 32 Mb (6.6 sigma) with a read current of 15 $\mu\mbox{A}$ and sensing time of 3.4 ns.

A graphite based STT-RAM cell with reduction in switching current

Spin Transfer Torque Random Access Memory (STT-RAM) is a serious candidate for “universal memory” because of its non-volatility, fast access time, high density, good scalability, high endurance and relatively low power dissipation. However, problems with low write speed and large write current are important existing challenges in STT-RAM design and there is a tradeoff between them and data retention time. In this study, a novel STT-RAM cell structure which uses perfect graphite based Magnetic Tunnel Junction (MTJ) is proposed. First, the cross-section of the structure is selected to be an ellipse of 45nm and 180nm dimensions and a six-layer graphite is used as tunnel barrier. By passing a lateral current with a short pulse width (before applying STT current and independent of it) through four middle graphene layers of the tunnel barrier, a 27% reduction in the amplitude of the switching current (for fast switching time of 2ns) or a 58% reduction in its pulse width is achieved without any reduction in data retention time. Finally, the effect of downscaling of technology on the proposed structure is evaluated. A reduction of 31.6% and 9% in switching current is achieved for 90 and 22nm cell width respectively by passing sufficient current (100µA with 0.1ns pulse width) through the tunnel barrier. Simulations are done using Object Oriented Micro Magnetic Framework (OOMMF).

Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory

A spintronic device, called the “strain assisted spin transfer torque (STT) random access memory (RAM),” is proposed by combining the magnetostriction effect and the spin transfer torque effect which can result in a dramatic improvement in the energy dissipation relative to a conventional STT-RAM. Magnetization switching in the device which is a piezoelectric-ferromagnetic heterostructure via the combined magnetostriction and STT effect is simulated by solving the Landau-Lifshitz-Gilbert equation incorporating the influence of thermal noise. The simulations show that, in such a device, each of these two mechanisms (magnetostriction and spin transfer torque) provides in a 90° rotation of the magnetization leading a deterministic 180° switching with a critical current significantly smaller than that required for spin torque alone. Such a scheme is an attractive option for writing magnetic RAM cells.

Achieving perpendicular anisotropy in half-metallic Heusler alloys for spin device applications

Various full Heusler alloys are interfaced with MgO and the magnetic properties of the Heusler-MgO junctions are studied. Next to MgO, the cubic Heusler system distorts to a tetragonal one, thereby inducing an anisotropy. The half-metallicity and nature of anisotropy (in-plane or perpendicular) in the Heusler-MgO system is governed mostly by the interface Heusler layers. There is a trend that Mn-O bonding near the MgO-Heusler junction results in perpendicular anisotropy. The ability to remain half-metallic and have perpendicular anisotropy makes some of these alloys potential candidates as free-layers in Spin Transfer Torque Random Access Memory (STT-RAM) devices, particularly, Cr2MnAs-MgO system with MnAs interface layers and Co2MnSi-MgO system with Mn2 interface layers.

Structural and magnetic properties of Cr-diluted CoFeB

The crystallization process and the magnetization of Cr diluted CoFeB were investigated in both ribbon samples and thin film samples with Cr content up to 30 at. %. A primary crystallization of bcc phase from an amorphous precursor in ribbon samples was observed when the annealing temperature rose between 421 °C and 456 °C, followed by boron segregation at temperatures between 518 °C and 573 °C. The two onset crystallization temperatures showed strong dependences on both Cr and B concentrations. The impact of Cr concentration on the magnetic properties including a reduced saturation magnetization and an enhanced coercive field was also observed. The magnetizations of both ribbon samples and thin film samples were well fitted using the generalized Slater-Pauling curve with modified moments for B (−0.94 μB) and Cr (−3.6 μB). Possible origins of the enhanced coercive field were also discussed. We also achieved a damping parameter in CoFeCrB thin films at the same level as Co40Fe40B20, much lower than the value reported for CoFeCrB films previously. The results suggest a possible advantage of CoFeCrB in reducing the critical switching current density in Spin Transfer Torque Random Access Memory.

Progress and Prospects of Spin Transfer Torque Random Access Memory

We report our progress on material improvement, device design, wafer processing, integration with CMOS, and testing of STT-RAM memory chips at 54 nm node with cell sizes of 14 and 28 F2 (F=54 nm). A dual tunnel barrier MTJ structure was found to have lower and more symmetric median spin transfer torque writing switching currents, and much tighter parallel to antiparallel switching current distribution. In-plane MTJ devices write endurance data, read and write soft error rates data and simulation fits, and solutions to the long write error rate tail at fast write speeds are discussed.

Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder

In this article, we propose a data storage system with the emerging nonvolatile memory technologies used for the implantable electrocardiography (ECG) recorder. The proposed storage system can record the digitalized real-time ECG waveforms continuously inside the implantable device and export the stored data to external reader periodically to obtain a long-term backup. Spin transfer torque random access memory (STT-RAM) and spintronic memristor are selected as the storage elements for their nonvolatility, high density, high reliability, low power consumption, good scalability, and CMOS technology compatibility. The new read and write schemes of STT-RAM and spintronic memristors are presented and optimized to fit the specific application scenario. The tradeoffs among data accuracy, chip area, and read/write energy for the different technologies are thoroughly analyzed and compared. Our simulation results show the configuration with a data sampling rate (e.g., 128 Hz) and a quantization resolution (e.g., 12 bits) can record 18-hour real-time data within ~ 3.6-mm 2 chip area when the data storage is built with single-level cell (SLC) STT-RAMs. Daily energy consumption is 5.46 mJ. Utilizing the multilevel cell (MLC) STT-RAMs or the spintronic memristors as the storage elements can further reduce the chip area and decrease energy dissipation.