Transfer Characteristics Of Thin-film Transistors Research Articles

DC sputtered ZrO2/Zn(1−x)Sn(x)O thin-film transistors and their property evaluation

A bottom gate staggered 30 nm Zn(1−x)Sn(x)O (x = 0.14) (TZO)-based thin-film transistors (TFTs) were fabricated using DC magnetron reactive sputtering method. Highly transparent 120 nm dc sputtered ZrO2 was used as a gate dielectric. The oxygen flow rate was varied from 20 to 24% during channel layer (TZO) coating and its effect on structural, morphological, optical, chemical, and electrical parameters were systematically studied. A nano scale roughness was noticed by atomic force microscopy (AFM), and ultra-smooth nature in root mean square roughness (RMS) was observed with an increment in the oxygen flow ratio. The increase in the oxygen-related defects with increase in the oxygen flow ratio in channel layer was evident from X-ray photoelectron spectroscopy (XPS). The electrical characterization of gate dielectric was carried out for Al–ZrO2–Al structure. The high capacitance density ~ 121.9 nF/cm2 for 120 nm ZrO2 was obtained from the capacitance–voltage (C–V) measurement. The fabricated TFTs operated in n-channel depletion mode and indicated pinch-off region at lower source–drain voltages. In addition, the transfer characteristics of TFTs confirmed Ion/Ioff ratio of 105, with a field effect mobility of 23 cm2/V.s. This low temperature processed TFT unlocks the possibility of use in the next generation foldable display technology.

Electrical Performance Enhancement of Fully Solution-processed Amorphous In-Zn-O Thin-Film Transistor via Argon Plasma Treatment

Amorphous oxide semiconductors are intensively studied nowadays due to its excellent material characteristics, such as high mobility, high optical transparency, large area uniformity, and low processing temperature which enable flexible device application [1]. Solution approach is a promising method over conventional vacuum process, because of its simplicity and versatility with high material utilization which can minimize fabrication cost [2]. To optimize for application in flexible substrates, reduction of process temperatures to <400oC is an important requirement. Plasma treatment can be used to modify thin-film properties and device characteristics by modulating carrier concentration and density of oxygen vacancies [3]. Argon plasma treatment can improve reliability, as carbon concentration on the surface can be reduced, and oxidation enhancement on the surface can be achieved. This research aims to study the effect of plasma treatment on the stability of fully solution processed amorphous Indium Zinc Oxide (a-IZO) thin-film transistor (TFT).Our fully solution processed a-IZO TFTs were fabricated with a self-aligned top gate structure at a maximum fabrication temperature of 300oC. Initially, IZO precursor was spin-coated on Si/SiO2 substrate. Then, fluorinated-polysilsesquioxane (F-PSQ) was deposited with a thickness of ~200 nm which act as a gate-insulator, followed by an IZO layer to be transformed as conducting electrode after treatment. Self-aligned patterning, gate etching, and gate insulator etching were then performed. Lastly, Argon plasma treatment is performed via inductively coupled plasma (ICP), using reactive ion etching SAMCO 10-ip equipment for 5 seconds at room temperature with an ICP power, bias power, and working pressure of 300 W, 100 W, and 5 Pa, respectively. The Argon flow rate was also varied at 100, 75, and 50 sccm. The IZO TFT without plasma treatment was denoted as-fabricated sample. After plasma treatment, exposed IZO layers transform as source/drain and gate. TFT structure before and after plasma treatment can be seen in Fig. 1.Film surface morphology was studied using atomic force microscopy. As Argon concentration increased, the exposed IZO surface became rougher. We also checked the transfer characteristics, performed cyclic measurement, and bias stress tests. Transfer characteristics of TFTs with 90µm width and 10µm length were examined at several drain voltages (Vd = 0.1 V, 5.0 V, and 9.9 V) by a semiconductor parameter analyzer. Transfer curves for as-fabricated and after Ar-75 plasma treatment are shown in Fig 1. As-fabricated sample shows poor switching characteristics because of inactivated source/drain and gate electrodes. After plasma treatment, TFTs show superb characteristics which possibly happened because of changes in the metal-oxide bond formation which increased the conductivity in exposed area. The mobility significantly increased to 31.12 cm2/Vs, with a Vth= -0.3 V and subthreshold swing of 0.28 V/dec for Ar-75 sccm. TFT yield was evaluated by measuring 8 TFTs for each sample. Average mobility for Ar-50, Ar-75, and Ar-100 is 20.30 cm2/Vs, 22.93 cm2/Vs, and 19.88 cm2/Vs, respectively. The mobility increase corresponded to the thin-film quality improvement caused by change in VO and surface roughness [4]. However, excessive Argon gas flow also tend to make samples more conductive.To investigate device stability, positive bias stress (PBS, stress V g= 10 V) and negative bias stress (NBS, stress V g= -10 V) was performed for 2,000s. Lower on-current for all samples were observed as bias stress duration increased. A threshold voltage shift (∆Vth) for Ar-50, Ar-75, and Ar-100 of 0.2 V, -0.3 V, and 0.6 V, respectively after PBS, and 1.4 V, 2.9 V, and 0.7 V, respectively after NBS was observed. We expect that improvement via plasma treatment is due to two main factors. First, ion bombardment caused surface improvement and activated the electrode. Second, the chemical reaction induced by plasma treatment changed the metal-oxide bonds formation [5-6]. Thus, fully solution-processed a-IZO TFT with high mobility up to 31.12 cm2/Vs was achieved by Ar-75 plasma treatment, which also led to better stability under bias stress. These results show that performance enhancement of fully-solution processed a-IZO TFT by plasma treatment has a large potential for future low-temperature flexible device applications.Acknowledgment:This research was supported by JSPS Kakenhi Grant no. 22K14291. The authors thank Nissan Chemical Corporation for providing the IZO precursor solution.

Low-temperature formation of high-mobility a-InGaZnOx films using plasma-enhanced reactive processes

This work demonstrated the low-temperature fabrication of high-mobility a-InGaZnOx (a-IGZO) films using plasma-enhanced reactive processing. The effect of the post-processing temperature on the performance of IGZO thin-film transistors (TFTs) using these a-IGZO films as a channel layer was also investigated. IGZO TFTs incorporating a-IGZO films plasma-treated at temperatures as low as 200 °C exhibited the expected TFT transfer characteristics, with field effect mobility values as high as 40 cm2 V−1 s−1. The fabrication of IGZO TFTs that exhibited homogeneous characteristics over large substrate areas was attempted, by assessing the effects of the plasma treatment on a-IGZO films deposited at various oxygen flow rate ratios. The electrical properties of IGZO TFTs using plasma-treated films were found to be dramatically improved, irrespective of the film deposition conditions prior to the plasma treatment. These results confirm the feasibility of producing IGZO TFTs with uniform characteristics over large substrates areas.

Correlation Between Currents, X-ray Diffraction Patterns and Transfer Characteristics of SnO₂ Thin Film Transistor.

SnO₂ thin film transistor (TFT) was prepared with SiOC as a gate insulator on n-type Si and the correlation between bonding structures, the contact properties of SnO₂ thin films and the transfer characteristics of TFTs was researched. The current of SnO₂ thin films increased with increasing the crystallinity and the crystallinity of SnO₂ was increased by annealing. The SnO₂ deposited with much oxygen gas flows became an amorphous structure after annealing due to lowered crystallinity. On the other hand, the current decreased in the amorphous structure SnO₂ with high oxygen vacancies. However, the ambipolar transfer characteristics of SnO₂/SiOC TFT with an amorphous structure had higher stability-mobility than that of TFT with the crystallinity, because of the increment effect of the diffusion current at the depletion layer as the amorphous structure with high Schottky barrier (SB).

Test System for Thin Film Transistor Parameter Extraction in Active Matrix Backplanes

Thin film transistor (TFT) active matrix backplanes are used in large area electronic systems, such as displays and image sensors. With backplanes being fabricated on wearable and flexible substrates, the possibilities of operational faults in backplanes have increased. These faults could either be hard faults, such as line opens or shorts or could be softer faults, such as time dependent variations in the TFT transfer characteristics. Real time diagnosis of these faults require built-in-self-test systems. While many such systems have been demonstrated to diagnose hard faults, an easily realizable system to identify soft faults, such as variations in transistor transconductance remain an open challenge. In this paper, we discuss a system that extracts the transconductance by charging and then discharging the pixel capacitor at various gate voltages for an active matrix liquid crystal display backplane. This permits a plot of the time averaged current versus the gate voltage from which the spatial variation of transconductance can be extracted. The details of the design are discussed and a proof of concept with a $3\times 4$ amorphous silicon backplane is demonstrated.

Fabrication of high-performance InGaZnOx thin film transistors based on control of oxidation using a low-temperature plasma

This work demonstrated the low-temperature control of the oxidation of Amorphous InGaZnOx (a-IGZO) films using inductively coupled plasma as a means of precisely tuning the properties of thin film transistors (TFTs) and as an alternative to post-deposition annealing at high temperatures. The effects of the plasma treatment of the as-deposited a-IGZO films were investigated by assessing the electrical properties of TFTs incorporating these films. A TFT fabricated using an a-IGZO film exposed to an Ar-H2-O2 plasma at substrate temperatures as low as 300 °C exhibited the best performance, with a field effect mobility as high as 42.2 cm2 V−1 s−1, a subthreshold gate voltage swing of 1.2 V decade−1, and a threshold voltage of 2.8 V. The improved transfer characteristics of TFTs fabricated with a-IGZO thin films treated using an Ar-H2-O2 plasma are attributed to the termination of oxygen vacancies around Ga and Zn atoms by OH radicals in the gas phase.

Analysis of Amorphous Indium-Gallium-Zinc-Oxide Thin-Film Transistors with Bi-Layer Gate Dielectric Stacks Using Maxwell-Wagner Instability Model

Aluminium oxide (Al2O3) and hafnium oxide (HfO2) have been grown, using atomic layer deposition (ALD), as single and bi-layer gate dielectric films. Electrical and structural characterisation indicates that the material properties depend on layer thickness and growth order, when deposited as bi-layers. Charge trapping at the interface between the bi-layer stacks results from the Maxwell-Wagner (MW) instability, which states a difference of conductivities at the dielectric-dielectric interface with respect to the bulk dielectric films. Hence a build-up of this interface charge compensates for the condition that the current densities of individual dielectric films match that of the overall stack. This causes electrical instabilities in stack behaviour. Bottom-gate amorphous indium-gallium-zinc-oxide thin-film transistors are fabricated with these gate oxides, single and bi-layer stacks, with low VTH and gate leakage current to understand this instability. By empirically adopting ideal MOSFET equations and single gate dielectric film behaviour as a reference, this MW instability in bi-layer gate dielectric stacks has been accounted for in amorphous indium-gallium-zinc-oxide thin-film transistor transfer characteristics with a good fit in both above threshold and sub-threshold regimes.

Analysis of Amorphous Indium-Gallium-Zinc-Oxide Thin-Film Transistors with Bi-Layer Gate Dielectric Stacks Using Maxwell-Wagner Instability Model

Aluminium oxide (Al2O3) and hafnium oxide (HfO2) have been grown, using atomic layer deposition (ALD), as single and bi-layer gate dielectric films. Electrical and structural characterisation indicates that the material properties depend on layer thickness and growth order, when deposited as bi-layers. Charge trapping at the interface between the bi-layer stacks results from the Maxwell-Wagner (MW) instability, which states a difference of conductivities at the dielectric-dielectric interface with respect to the bulk dielectric films. Hence a build-up of this interface charge compensates for the condition that the current densities of individual dielectric films match that of the overall stack. This causes electrical instabilities in stack behaviour. Bottom-gate amorphous indium-gallium-zinc-oxide thin-film transistors are fabricated with these gate oxides, single and bi-layer stacks, with low VTH and gate leakage current to understand this instability. By empirically adopting ideal MOSFET equations and single gate dielectric film behaviour as a reference, this MW instability in bi-layer gate dielectric stacks has been accounted for in amorphous indium-gallium-zinc-oxide thin-film transistor transfer characteristics with a good fit in both above threshold and sub-threshold regimes.

(Invited) Instability Mechanisms in Amorphous Oxide Semiconductors Leading to a Threshold Voltage Shift in Thin Film Transistors

Amorphous indium gallium zinc oxide (a-IGZO) has been successfully employed commercially as the channel layer in thin film transistors (TFTs) for active-matrix flat panel displays. However, these TFTs are known to suffer from a threshold voltage shift upon application of a gate bias. The threshold voltage shift is reversible through annealing. A similar phenomenon is observed in other TFTs with an amorphous oxide semiconductor channel. The migration of oxygen vacancies is proposed as being the microscopic mechanism causing this effect as it can lead to a change in the equilibrium distribution of defect states in the band gap of the semiconductor. This would manifest itself as a reversible threshold voltage shift in the TFT transfer characteristics, as observed experimentally.

Influence of Carrier Concentration at Front- and Back-Channel on Transfer Characteristics of Bottom-Gate Ιn-Ga-Zn-O Thin-Film Transistors

High drain current (I DS) is required for thin-film transistors (TFTs) to drive next-generation high-definition and large-screen flat panel displays (FPDs). An In-Ga-Zn-O (IGZO) TFT has received considerable attention for the next-generation FPDs because it has high electron mobility (µ >10 cm2V-1s-1) and large area uniformity [1]. Previously, we reported that the I DS and an apparent field-effect mobility (µ FE) of IGZO TFT was enhanced owing to a reduction of an effective channel length (L eff) when the sheet carrier concentration (N s) at back-channel interface increased [2]. However, it has not clarified the influence of carrier concentration at either front- or back-channel on transfer characteristics of the IGZO TFT. In this research, an influence of N s at front- and back-channel on transfer characteristics of bottom-gate IGZO TFT was analysed by device simulator (ATLAS). First, physical parameters of the IGZO TFT was defined to reproduce the transfer characteristics of actual fabricated TFT which was used as reference [3] (denoted hereafter as ref.-TFT). Next, a thin layer, that was modulated the N s from 6.8×1011 to 2.5×1014 cm-2, was set at the back-channel region of the TFT as shown in Fig.1 (a) (denoted hereafter as MD-TFTs). Fig.1 (b) shows the comparison of transfer characteristics of the TFTs. From Fig.1 (b), the I DS of MD-TFTs drastically increased as compared with the ref.-TFT. In addition, it can be seen that the I DS enhancement was increased with increasing N s at back-channel. From these I DS enhancement, an apparent µ FE calculated from transfer characteristics enhanced for the MD-TFTs as shown in Fig1 (c). For the case of the N s was 6.8×1011 cm-2, an apparent µ FE was increased to 29.8 cm2V-1s-1 for sub-threshold region, whereas an apparent µ FE was almost the same as ref.-TFT at on (V GS=+20 V) region. When the N s further increased to 2.5×1013 cm-2, the overestimation of an apparent µ FE was observed for both sub-threshold and on (V GS=+20 V) region. To investigate the reason for changing apparent µ FE of MD-TFT with 6.8×1011 cm-2 with gate-voltage, current density in MD-TFT with N s of 6.8×1011 cm-2 was simulated as shown Figs.2 (a) and 2 (b). In case of sub-threshold region (V GS=+3 V), the L eff at front-channel interface drastically reduce as compared with the mask-defined channel length (L m). On the other hand, the L eff at the on (V GS=+20 V) region was unchanged to the L m. As a consequence of reduction of the L eff, it was increased to apparent µ FE of MD-TFT with 6.8×1011 cm-2 at the sub-threshold region. These results suggested that N s difference between back- and front-channel interfaces are strongly related to the carrier transport mechanism in MD-TFTs, because the carrier transport path was changed by increasing N s at front-channel with gate-voltage. As a results of further analysis by device simulator, it was revealed that the enhancement of I DS and an apparent µ FE were induced owing to the difference of N s between back- and front-channel interfaces. Detail of the results will be presented at the conference. [1] T. Kamiya, K. Nomura and H. Hosono, “Present status of amorphous In-Ga-Zn-O thin-film transistors” Sci. Technol. Adv. Mater, Vol.11, pp.044305-044328, Sept. 2010. [2] D. Koretomo, T. Toda, D. Wang and M.Furuta, “Anomalous Increase of Field-Effect Mobility in In-Ga-Zn-O Thin-Film Transistors Caused by Dry-Etching Damage Through Etching-Stopper” presented at 35-4, 15th Int. Conf. IMID, 2015.[3] Mutsumi Kimura, “Practical Guidance of Parameter Extraction for Device Simulation of Thin-Film Transistors”, J. Appl. Phys., vol.51, pp.054302-1-054302-5, April 2012 Figure 1

Carrier transport across grain boundaries in polycrystalline silicon thin film transistors

We established a model for investigating polycrystalline silicon (poly-Si) thin film transistors (TFTs). The effect of grain boundaries (GBs) on the transfer characteristics of TFT was analyzed by considering the number and the width of grain boundaries in the channel region, and the dominant transport mechanism of carrier across grain boundaries was subsequently determined. It is shown that the thermionic emission (TE) is dominant in the subthreshold operating region of TFT regardless of the number and the width of grain boundary. To a poly-Si TFT model with a 1 nm-width grain boundary, in the linear region, thermionic emission is similar to that of tunneling (TU), however, with increasing grain boundary width and number, tunneling becomes dominant.

Role of oxygen vacancies on the bias illumination stress stability of solution-processed zinc tin oxide thin film transistors

Solution-processed ultra-thin (∼3 nm) zinc tin oxide (ZTO) thin film transistors (TFTs) with a mobility of 8 cm2/Vs are obtained with post spin-coating annealing at only 350 °C. The effect of light illumination (at wavelengths of 405 nm or 532 nm) on the stability of TFT transfer characteristics under various gate bias stress conditions (zero, positive, and negative) is investigated. It is found that the ΔVth (Vthstress 3400 s − stress 0 s) window is significantly positive when ZTO TFTs are under positive bias stress (PBS, ΔVth = 9.98 V) and positive bias illumination stress (λ = 405 nm and ΔVth = 6.96 V), but ΔVth is slightly negative under only light illumination stress (λ = 405 nm and ΔVth = −2.02 V) or negative bias stress (ΔVth = −2.27 V). However, the ΔVth of ZTO TFT under negative bias illumination stress is substantial, and it will efficiently recover the ΔVth caused by PBS. The result is attributed to the photo-ionization and subsequent transition of electronic states of oxygen vacancies (i.e., Vo, Vo+, and Vo++) in ZTO. A detailed mechanism is discussed to better understand the bias stress stability of solution processed ZTO TFTs.

Influence of Gate Corrugations on the Performance of Thin-Film Transistors

This letter investigates the influence of a corrugated gate on the transfer characteristics of thin-film transistors. Corrugations that run parallel to the length of the channel from source to drain are patterned on the gate. The author finds that these corrugations result in higher currents as compared to conventional planar-gate transistors.

Reduction of Hot Carrier Effects in Silicon-on-Glass TFTs

Hot carrier (HC) instability of thin-film transistors (TFTs) fabricated on single-crystal,silicon-on-glass (SiOG) substrates is studied. The formation of the SiOG substrate is achieved by the transfer of a single-crystal silicon film to a display-glass substrate. The transfer process creates an in-situ barrier layer free of mobile ions in the glass adjacent the silicon film. The n- and p-channel TFT transfer characteristics typically exhibit excellent on-state performance with gate voltage swing values of 180 mV/decade, electron and hole mobilities of ∼ 251 and 201 cm2/V·s respectively, and threshold voltages of approximately −0.3 and −1.2 V for the n- and p-channel TFT’s respectively. While p-channel TFTs exhibit good stability, on-current degradation is observed in the transfer characteristics of the n-channel TFT. The degradation is due to HC stress. In this study, the integration of a lightly doped drain (LDD) structure in the n-channel SiOG TFTs to minimize HC instability is reported. The LDD design incorporates 2 μm offset regions. The offset regions are lightly doped (n-) with phosphorus ions implanted at 10 keV. N-levels of ∼ 1 × 1013, 2 × 1013, and 3 × 1013 cm−2 are analyzed to determine the optimum doping conditions that reduce HC instability while minimizing degradation in the on-state device performance.

Reduction of Hot Carrier Effects in Corning Silicon-on-Glass TFTs

Hot carrier (HC) instability of thin film transistors (TFTs) fabricated on single crystalline Corning® Silicon-on-Glass (SiOG) substrates is studied (1). The n- and p-channel TFT transfer characteristics typically exhibit excellent on-state performance with electron and hole field effect mobilities (μfe) of ~251 and 201 cm2/V⋅s, threshold voltages of ~-0.3 and -1.2 V, and gate swing (S) values of ~180 mV/dec. While p-channel TFTs exhibit good stability, on-current (ION) degradation is unfortunately observed in the transfer characteristics of the n-channel TFT due to HC stress. In this study, the integration of a lightly doped drain (LDD) structure to minimize HC instability in the n-channel SiOG TFTs is reported. The LDD design has 2 μm regions produced by ion implanting phosphorus at 10 keV to a light doping (n-) level. N- levels of ~1 × 1013, 2 × 1013, and 3 × 1013 cm−2 are analyzed to determine the optimum doping conditions that leads to HC improvement with minimal detrimental impact to the on-state device performance.

Reduction of Off-State Currents in Silicon on Glass Thin Film Transistor by Off-State Bias Stress

We have studied the impact of off-bias stress on the performance of thin film transistors (TFTs) fabricated on single crystalline silicon-on-glass substrates. The p-channel TFT transfer characteristics typically exhibit excellent on-state performance with a field-effect mobility of 203 cm 2 /V s and a subthreshold swing of around 200 mV/dec. However, the off-state drain current has increased with increasing gate voltage. This increasing off-state current phenomenon can be significantly reduced by performing an off-state bias for 10 s. The formation of electron traps in the gate oxide near the drain is the main factor that reduces the off-state leakage current.

Nonvolatile memory based on sol-gel ZnO thin-film transistors with Ag nanoparticles embedded in the ZnO/gate insulator interface

A nonvolatile memory is demonstrated using a solution-processed sol-gel ZnO thin-film transistor (TFT) in which Ag nanoparticles are embedded as charge storage nodes at the insulator-ZnO interface. Its TFT transfer characteristics exhibit a large clockwise hysteresis that is proportional to the gate bias sweep range. Measurement of the threshold voltage shift versus the pulse width of gate bias reveals that the device can be programed or erased at a time scale of as short as 10−4 s. Retention of the initial memory window is measured to be 27% after 105 s and projected to last until 107 s.

Effects of Electrical Bias Stress on the Performance of ZnO -Based TFTs Fabricated by RF Magnetron Sputtering

-based thin film transistors (TFTs) were fabricated on a tin oxide (ITO)/glass substrate by radio frequency (rf) magnetron sputtering at . The transfer characteristics of the fabricated TFT showed a drain current on/off ratio of , a field effect mobility of , an off current lower than , and a threshold voltage of . The stability of the TFTs was examined under various electrical bias stress conditions. The operation of TFT was stable at the electrical bias stress ( at , ) for stress time of . However, with increasing bias stress and the duration of the stress, the transfer characteristics of TFT were degraded, and the devices were physically damaged due to heavy charge accumulation in the channel layer. In addition, trapping of tunneling electrons in the caused threshold voltage shift.

Poly-Si TFTs From Glass to Plastic Substrates: Process and Manufacturing Challenges

AbstractPoly-Si Thin-Film Transistors (TFTs) are currently used in commercial active-matrix displays. They provide superior performance with respect to their amorphous silicon counterparts and allow integration of driving electronics directly on the display glass plates.For several applications, it can be desirable to have active-matrix displays made on flexible substrates. However, a direct application of a standard TFT process to plastic substrates is not in general possible, mostly because of temperature limits and related dimensional stability issues. In addition, standard flat-panel manufacturing tools are not capable of automatically handling non-rigid floppy substrates.Therefore, a new process has to be developed, compatible with a suitable way of handling plastic substrates. A process was developed in which plastic sheets are laminated on glass carrier wafers and run through all the automated tools. A low-temperature process using excimer laser annealing is developed and optimized. High-quality TFT backplanes are manufactured with a pixel layout designed for active-matrix OLED (AMOLED) displays. Field-effect mobility in excess of 70 cm2Vs on p-channel TFTs are achieved, together with leakage currents lower than 2 pA per micron gate width.Challenges include low-temperature gate dielectric development, reduction of intrinsic film stress, protection of plastic from laser damage, and contact formation. Solutions to these challenges are discussed and TFT transfer characteristics on glass and plastic substrates are presented. Finally, images from prototype monochrome AMOLED displays are presented, with 64 × 64 pixels and 80-dpi resolution.

Switch-On Transients And Static Characteristics Of Polymorphous And Amorphous Silicon Thin-Film Transistor

AbstractHydrogenated polymorphous silicon (Pm-Si:H) being an admixture of amorphous and ordered phase silicon shows improved optical and electrical properties due to the presence of nanocrystallites. In order to compare the dynamic and steady state electrical properties in a-Si:H and pm-Si:H, bottom gate Thin Film Transistors (TFT) of these materials were fabricated with SiO2 as the insulating layer. The active materials were deposited using plasma-enhanced chemical vapor deposition (PECVD) by varying pressure, temperature and hydrogen dilution. Transfer characteristics of TFTs made using pm-Si:H show lower leakage current, higher on-current and sharper volt per decade change as compared to similar TFTs made from a-Si:H. Density of states in pm-Si:H as calculated from field effect conductance using incremental method is observed to be an order of magnitude lower than in a-Si:H based devices. To compare dynamic characteristics, we studied the switch-on transient characteristics of polymorphous and amorphous silicon TFTs by pulsing the gate to different voltages in the temperature range of 150-300K. The switch-on transients are trap limited with overall better switching characteristics for pm-Si:H samples. An initial rising transient in case of pm-Si:H is activated with an effective energy of 0.3 eV. The origins of transients are interpreted in terms of trap limited carrier dynamics and charge redistribution within the distribution of localized states.