Transconductance Curves Research Articles

Machine learning based prediction of I–V and transconductance curves for 3D multichannel junctionless FinFET

Machine learning based prediction of I–V and transconductance curves for 3D multichannel junctionless FinFET

Strong contact resistance effects on vertical carrier density profile and surface trap density in WSe2 multilayers

Conducting channel migration depending on the thickness of 2D multilayers has been demonstrated theoretically and experimentally by ascribing it to the high interlayer barrier and thickness-dependent carrier mobility via an electrostatic gate and drain bias. However, the unique charge carrier transport feature is significantly suppressed when a high contact resistance is exhibited at the metal-to-2D semiconducting multilayers, in addition to the inherent tunneling barrier between neighboring layers. Herein, we report strong channel access contact resistance effects on the vertical carrier density profile and surface trap density along the thickness of WSe2 multilayer transistors. For the constructed top-contact electrodes demonstrating pseudo-ohmic behavior, we observed clear double humps in the second derivative of the transconductance (dgm) curves, implying conducting channel migration along the c-axis of the WSe2 multilayers, regardless of the drain bias (VD) conditions. Meanwhile, at the bottom-contact electrodes, demonstrating a relatively high contact resistance effect, the second hump of dgm exclusively appears at high VD regimes (3.0 V ≤ VD), signaling the restricted channel migration caused by poor contact quality, even in identical WSe2 multilayers. We further confirmed this distinct feature in dgm curves by connecting the top and bottom electrodes to support our observations. Furthermore, low-frequency noise measurements were performed to determine the surface trap density of the supporting dielectrics and the relevant carrier scattering mechanism. Our study provides valuable insight into the effects of contact resistance on carrier transport and the scattering mechanism in WSe2 multilayer transistors, shedding light on the optimization of device performance and contact quality.

Study of the AlPN/GaN high electron mobility transistors with improved transconductance linearity

In this work, an improved method of metal-organic chemical vapor deposition was utilized to grow high-quality AlPN/GaN heterostructures. The characteristics of AlPN those are essential to achieving high linearity in the resulting devices were then investigated. High linearity AlPN/GaN high electron mobility transistors (HEMTs) with flatter transconductance curves were fabricated, in which the gate voltage swings are 1.85 and 4.35 V at 300 and 400 K when Gm drops 5% from Gm,max. Additionally, the impact of P anti-site defects and surface states on the high linearity of AlPN/GaN HEMTs at different temperatures was discussed. It was found that while both factors benefit linearity at room temperature, only the P anti-site defects have a positive effect on linearity at high temperatures. The results demonstrate the significant advantages of AlPN-based structures in high linearity device applications and provide instructive principles for improving linearity.

Hidden surface channel in two-dimensional multilayers

Numerous carrier scatterers, such as atomic defects, fixed oxide charges, impurities, chemical residues, and undesired surface adsorbates, including oxygen and water molecules, strongly degrade the carrier mobility of atomically thin two-dimensional (2D) materials. However, the effect of surface adsorbates and surface oxidation on the carrier density profile along the thickness of 2D multilayers is not well known, particularly for a substantial interruption in the formation of the top-surface channel. Here, we uncover a hidden surface channel in p-type black phosphorus and n-type rhenium disulfide multilayers originating from undesired ambient adsorbates and surface oxides that not only populate hole density (or reduce electron density) but also suppress carrier mobility. The absence of a second peak in the transconductance curve under ambient conditions indicates the disappearance of the top-surface channel inside the 2D multilayers, which is a possible indicator for the cleanliness of the top surface and can be used in gas sensor applications. Moreover, the negligible variation in the drain bias polarity-dependent turn-on voltage for the bottom channel under ambient conditions validates the exclusive contribution of surface adsorbates to the formation of the top channel in 2D multilayers. Our results provide a novel insight into the distinct carrier transport in 2D optoelectronic devices and diverse sensors.

Unexpected Electron Transport Suppression in a Heterostructured Graphene-MoS2 Multiple Field-Effect Transistor Architecture.

We demonstrate a graphene–MoS2 architecture integrating multiple field-effect transistors (FETs), and we independently probe and correlate the conducting properties of van der Waals coupled graphene–MoS2 contacts with those of the MoS2 channels. Devices are fabricated starting from high-quality single-crystal monolayers grown by chemical vapor deposition. The heterojunction was investigated by scanning Raman and photoluminescence spectroscopies. Moreover, transconductance curves of MoS2 are compared with the current–voltage characteristics of graphene contact stripes, revealing a significant suppression of transport on the n-side of the transconductance curve. On the basis of ab initio modeling, the effect is understood in terms of trapping by sulfur vacancies, which counterintuitively depends on the field effect, even though the graphene contact layer is positioned between the backgate and the MoS2 channel.

490 mA/mm drain current and 1.9 V threshold voltage enhancement-mode p-GaN HEMTs and high-temperature characteristics

In this paper, enhancement-mode AlGaN/GaN p-type GaN cap layer high electron mobility transistors (p-GaN HEMTs) with Ti/Au gate metal are fabricated and electrically characterized. The post gate annealing (PGA) treatment at 300 °C for 10 min is utilized to improve the devices’ characteristics. As a result, the p-GaN HEMTs achieve a high drain current (IDS) of 490 mA/mm at VGS = 7 V with a high threshold voltage (VTH) of 1.9 V. Meanwhile, the pulse measurements show good dynamic characteristics, and the temperature-dependent characteristics indicate that the VTH has excellent high-temperature stability from 25 °C to 175 °C. Besides, it can be found that the temperature will affect the capacitance–voltage (C-V) and transconductance curves, which is related to the hole energy and electron mobility at different temperatures.

Highly scaled graded channel GaN HEMT with peak drain current of 2.48 A/mm

The dc and high frequency performances of Al composition Graded Channel AlGaN/GaN high electron mobility transistor on GaN substrate was investigated and compared with Conventional AlGaN/GaN HEMT. The high frequency characteristics were measured on both the AlGaN/GaN HEMTs scaling the gate length from 800 nm to 50 nm. The 50 nm gate length Graded Channel AlGaN/GaN HEMT exhibited the highest drain current of 2.48 A/mm and transconductance of 0.32 S/mm respectively at a drain voltage of VD = 10 V. Also the transconductance curve of the Graded Channel HEMT is flatter than that of conventional GaN HEMT. The flatter transconductance curve reduces the power gain roll off in Graded Channel HEMT and thus gives improved performance in terms of device linearity. The current gain cutoff frequency fT = 126.5 GHz was obtained for the Graded Channel HEMT at a gate length of 50 nm. This accounts to 61.6% increase in fT when compared to conventional GaN HEMT at the same gate length of 50 nm.

Restricted Channel Migration in 2D Multilayer ReS2.

When thickness-dependent carrier mobility is coupled with Thomas-Fermi screening and interlayer resistance effects in two-dimensional (2D) multilayer materials, a conducting channel migrates from the bottom surface to the top surface under electrostatic bias conditions. However, various factors including (i) insufficient carrier density, (ii) atomically thin material thickness, and (iii) numerous oxide traps/defects considerably limit our deep understanding of the carrier transport mechanism in 2D multilayer materials. Herein, we report the restricted conducting channel migration in 2D multilayer ReS2 after a constant voltage stress of gate dielectrics is applied. At a given gate bias condition, a gradual increase in the drain bias enables a sensitive change in the interlayer resistance of ReS2, leading to a modification of the shape of the transconductance curves, and consequently, demonstrates the conducting channel migration along the thickness of ReS2 before the stress. Meanwhile, this distinct conduction feature disappears after stress, indicating the formation of additional oxide trap sites inside the gate dielectrics that degrade the carrier mobility and eventually restrict the channel migration. Our theoretical and experimental study based on the resistor network model and Thomas-Fermi charge screening theory provides further insights into the origins of channel migration and restriction in 2D multilayer devices.

Design of Ga2O3 modulation doped field effect transistors

The design of β-Ga2O3-based modulation-doped field effect transistors is discussed with a focus on the role of self-heating and resultant modification of the electron mobility profile. Temperature- and doping-dependent model of the electron mobility as well as temperature- and orientation-dependent approximations of the thermal conductivity of β-Ga2O3 are presented. A decrease in drain current was attributed to a position-dependent mobility reduction caused by a coupled self-heating mechanism and a high electric-field mobility reduction mechanism. A simple thermal management solution is presented where heat is extracted through the source contact metal. Additionally, it is shown that an undesired secondary channel can form at the modulation-doped layer that is distinguished by an inflection in the transconductance curve.

A Fractional Drift Diffusion Model for Organic Semiconductor Devices

Because charge carriers of many organic semiconductors (OSCs) exhibit fractional drift diffusion (Fr-DD) transport properties, the need to develop a Fr-DD model solver becomes more apparent. However, the current research on solving the governing equations of the Fr-DD model is practically nonexistent. In this paper, an iterative solver with high precision is developed to solve both the transient and steady-state Fr-DD model for organic semiconductor devices. The Fr-DD model is composed of two fractional-order carriers (i.e., electrons and holes) continuity equations coupled with Poisson’s equation. By treating the current density as constants within each pair of consecutive grid nodes, a linear Caputo’s fractional-order ordinary differential equation (FrODE) can be produced, and its analytic solution gives an approximation to the carrier concentration. The convergence of the solver is guaranteed by implementing a successive over-relaxation (SOR) mechanism on each loop of Gummel’s iteration. Based on our derivations, it can be shown that the Scharfetter–Gummel discretization method is essentially a special case of our scheme. In addition, the consistency and convergence of the two core algorithms are proved, with three numerical examples designed to demonstrate the accuracy and computational performance of this solver. Finally, we validate the Fr-DD model for a steady-state organic field effect transistor (OFET) by fitting the simulated transconductance and output curves to the experimental data.

Effect of interlayer tunneling barrier on carrier transport and fluctuation in multilayer ReS2

Multilayer rhenium disulfide (ReS2) has recently attracted significant attention because of the decoupled van der Waals interaction between its adjacent layers that leads to a much higher interlayer resistivity than that in other layered materials. Although the carrier transport in multilayer materials is well described by the interlayer resistance and Thomas–Fermi charge screening length (λ) in theoretical resistor network models, the understanding of the effect of electric field-dependent interlayer tunneling barrier (Eint) on current fluctuation in two-dimensional (2D) multilayer materials is limited. Herein, we report the effects of Eint on carrier transport and charge fluctuation in multilayer ReS2. The electrostatic back-gate (VBG)- and drain bias (VD)-dependent Eint causes channel migration along the c-axis in 2D multilayer systems and consequently results in two plateaus in the transconductance curve, thereby allowing us to determine the top and bottom carrier mobilities of multilayer ReS2 separately. Furthermore, the strong correlation between Eint and the Coulomb scattering parameter in multilayer ReS2 is elucidated via low-frequency noise spectroscopy. The results of our study provide a clear insight into the origins of carrier transport and current fluctuation in 2D multilayer devices.

Impact of Gate Dielectric Material on Basic Parameters of MO(I)SHEMT Devices

Recently the high electron mobility transistors (HEMT) have drawn the attention of the scientific community for power electronic applications thanks to their wide bandgap and consequently high breakdown voltage (1-3). A new metal oxide/insulator semiconductor high electron mobility transistor (MOSHEMT) appears in order to minimize the leakage current as reported in (4). In this work, the basic parameters of MOSHEMT are evaluated experimentally for different gate insulators (10nm of Al2O3 and 5nm of SiNx).From the transfer curves presented in figure 1, one can notice a shift in the threshold voltage and different hysteresis behavior when comparing both insulators. The hysteresis analysis shows a better behavior for SiNx devices, which present negligible hysteresis values. Figure 2 presents the hysteresis width extracted from devices with Al2O3 as a function of gate length for different drain bias. Although usually the Vth variation is associated with positive charge trapping, which causes a negative Vth shift, in this case the opposite Vth variation was observed. This positive Vth shift may also be related with a degradation of the on-resistance, i.e., a higher voltage is required to obtain the same current level, as reported in (3). As the drain voltage and consequently the drain current increase, the Vth shift becomes smaller reducing the hysteresis values, as can be seen in figure 2.Focusing on the threshold voltage variation between devices with different gate dielectrics, although both the gate insulator thicknesses and the permittivity impact on the threshold voltage (Vth) of the transistor in opposite direction (5), the dominant factor of the Vth shift, in this case, is a negative linear relation between Vth and the dielectric thicknesses. The MISHEMT with 5 nm of SiNx presents a Vth almost 2V higher than MOSHEMT with 10nm of Al2O3.In addition to the better Vth value (closest to the normally-off device), SiNx dielectric transistors are less affected by the short channel effect (SCE) when compared to devices with Al2O3, as can be observed in figure 3. From Fig. 3 it is possible to notice that reducing the channel length (Lg) from 600nm to 200nm, the threshold voltage for transistors with SiNx dielectric (figure 3B) drops 175mV while for devices with Al2O3 layer (figure 3A) this reduction reaches 450mV. Considering DIBL (|Vthlinear – Vthsat|/ VDSsat – VDSLinear) with VDSsat=2V, it is also observed that for both splits the DIBL starts to degrade for Lg = 400 nm, however the values and the degradation of DIBL are much higher for devices with Al2O3 than for devices with SiNx dielectric. This behavior can be related to the thinner dielectric and better coupling between the gate and the GaN layer.When the MOSHEMTs were evaluated at high temperatures (from 25ºC to 150ºC), two different behaviors were obtained. The transfer characteristic of MOSHEMT with Al2O3 layer (figure 4A) presents an expected behavior, showing the zero temperature coefficient point (VZTC) due to the competition between the threshold voltage reduction and mobility degradation, while for the MISHEMTs with SiNx layer the VZTC was not found. In order to explain this unexpected behavior the threshold voltage and transconductance were evaluated (figures 5 and 6).MOSHEMTs with Al2O3 gate present a reduction of the threshold voltage as the temperature increases (figure 5A) due to the reduction of the fermi potential, for all analyzed channel lengths. However, for SiNx MISHEMTs Vth is reduced when the temperature increases from 25ºC to 50ºC, but for higher temperatures Vth starts to increase again creating a rebound effect. The threshold voltage anomalous behavior can be explained by the double conduction of the device which leads us to extract an effective Vth. This double conduction can only be observed when we evaluate the transconductance curve of the MISHEMTs (figure 6). It is possible to observe that for temperatures higher than 50ºC the transconductance curve presents two different slopes before the maximum value, representing two different conduction channels. Figure 6B shows the transconductance and drain current as a function of gate voltage at 100ºC and it is easy to see the two different slopes representing the two different threshold voltages, due to the turn on/off of the SiNx/AlGaN inversion layer. Looking for the transition point between both conductions, we can also observe a small peak in the drain current. Figure 1

Transport-map analysis of ionic liquid-gated ambipolar WSe2 field-effect transistors

We present the electrical characteristics of ionic liquid-gated ambipolar WSe2 field-effect transistors (FET) and analyze them graphically using a transport map. With the transport map, the ambipolar I–V characteristics, which have either electrons or holes as the majority charge carriers depending on the bias conditions, were easily divided into the electron and hole conduction regimes. The effect of the drain bias (Vd) on trapped charges is inferred from the decreased offset voltage, which indicates the downward deflection of the channel energy band with the Vd. We confirmed the change of the majority carrier types shown in the transport map by analyzing the output curves, which show a transition from rectifying to saturated behavior. The existence of a relatively thin Schottky barrier for hole conduction is supported by the degradation in the transconductance curves and the variation in Vth with the Vd. These results provide important information for understanding the operating mechanism of ambipolar WSe2 FETs gated by ionic liquids and can be extended to FETs based on other two-dimensional semiconducting materials.

Probing Distinctive Electron Conduction in Multilayer Rhenium Disulfide.

Charge carrier transport in multilayer van der Waals (vdW) materials, which comprise multiple conducting layers, is well described using Thomas-Fermi charge screening (λTF ) and interlayer resistance (Rint ). When both effects occur in carrier transport, a channel centroid migrates along the c-axis according to a vertical electrostatic force, causing redistribution of the conduction centroid in a multilayer system, unlike a conventional bulk material. Thus far, numerous unique properties of vdW materials are discovered, but direct evidence for distinctive charge transport behavior in 2D layered materials is not demonstrated. Herein, the distinctive electron conduction features are reported in a multilayer rhenium disulfide (ReS2 ), which provides decoupled vdW interaction between adjacent layers and much high interlayer resistivity in comparison with other transition-metal dichalcogenides materials. The existence of two plateaus in its transconductance curve clearly reveals the relocation of conduction paths with respect to the top and bottom surfaces, which is rationalized by a theoretical resistor network model by accounting of λTF and Rint coupling. The effective tunneling distance probed via low-frequency noise spectroscopy further supports the shift of electron conduction channel along the thickness of ReS2 .

Device behaviour and zero temperature coefficients analysis for microwave GaAs HEMT

Detailed analysis of device behaviour on the zero-temperature coefficient (ZTC) points for microwave GaAs based high-electron mobility transistor is presented by means of on-wafer measurements over the temperatures between −40 and 150 °C. This zero temperature coefficient points found not only in the transfer and transconductance curve but also in intrinsic transconductance gmo, output conductance gds, small signal gain S21, and minimum noise figure NFmin also exhibits ZTC. It is found that the zero temperature coefficients points are impacted by both threshold voltage and drain bias. The transfer current base, ZTCIds moved from 0.1 V to −0.2 V of Vgs trace and transconductance based, ZTCgm moved from −0.3 V to −0.6 V of Vgs trace with the drain bias, Vds varies from 1 V to 5 V. The behaviour of some intrinsic equivalent circuit parameters along with cut-off frequency, ft at both ZTC bias points opens some crucial insight and opportunities in microwave device design for low and high temperature applications.

Influence of disorder on transfer characteristics of organic electrochemical transistors

Organic electrochemical transistors (OECTs) are receiving a great deal of attention as transducers of biological signals due to their high transconductance. A ubiquitous property of these devices is the non-monotonic dependence of transconductance on gate voltage. However, this behavior is not described by existing models. Using OECTs made of materials with different chemical and electrical properties, we show that this behavior arises from the influence of disorder on the electronic transport properties of the organic semiconductor and occurs even in the absence of contact resistance. These results imply that the non-monotonic transconductance is an intrinsic property of OECTs and cannot be eliminated by device design or contact engineering. Finally, we present a model based on the physics of electronic conduction in disordered materials. This model fits experimental transconductance curves and describes strategies for rational material design to improve OECT performance in sensing applications.

Selective detection of dopamine with an all PEDOT:PSS Organic Electrochemical Transistor.

An all PEDOT:PSS Organic Electrochemical Transistor (OECT) has been developed and used for the selective detection of dopamine (DA) in the presence of interfering compounds (ascorbic acid, AA and uric acid, UA). The selective response has been implemented using a potentiodynamic approach, by varying the operating gate voltage and the scan rate. The trans-conductance curves allow to obtain a linear calibration plot for AA, UA and DA and to separate the redox waves associated to each compound; for this purpose, the scan rate is an important parameter to achieve a good resolution. The sensitivities and limits of detection obtained with the OECT have been compared with those obtained by potential step amperometric techniques (cyclic voltammetry and differential pulse voltammetry), employing a PEDOT:PSS working electrode: our results prove that the all-PEDOT:PSS OECT sensitivities and limits of detection are comparable or even better than those obtained by DPV, a technique that employs a sophisticate potential wave and read-out system in order to maximize the performance of electrochemical sensors and that can hardly be considered a viable readout method in practical applications.

Enhanced channel hot carrier effect of 0.13 m silicon-on-insulator N metal-oxide-semiconductor field-effect transistor induced by total ionizing dose effect

In this paper, a series of hot carriers tests of irradiated 130 nm partially depleted silicon-on-insulator NMOSFETs is carried out in order to explore the HCI influence on the ionizing radiation damage. Some devices are irradiated by up to 3000 Gy before testing the hot carriers, while other devices experience hot carriers test only. All the devices we used in the experiments are fabricated by using a 130 nm partially depleted (PD) SOI technology. The devices each have a 6nm-thick gate oxide, 100 nm-thick silicon film, and 145 nm-thick buried oxide, with using shallow trench isolation (STI) for isolation scheme. The irradiation experiments are carried by 60Co- ray at the Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences, with a dose rate of 0.8~Gy(Si)/s. During irradiation all the samples are biased at 3.3V, i.e., VGS=3.3V and other pins are grounded, and when the devices are irradiated respectively by total doses of 500, 1000, 2000 and 3000Gy(Si), we test the characteristic curves again. Then 168-hour room temperature anneal experiments are carried out for the irradiated devices, using the same biases under irradiation. The HCI stress condition is chosen by searching for the maximum substrate current. The cumulative stress time is 5000s, and the time intervals are 10, 100, 500, 1000 and 5000s respectively. After each stress interval, the device parameters are measured until stress time termination appears. Through the comparison of characteristic between pre-irradiated and unirradiated devices, we find that the total dose damage results in the enhanced effect of hot carriers: the substrate current value which characterizes the hot carrier effect (for SOI device are the body to the ground current) increases with the increase of total dose, as the pre-irradiated and unirradiated device do under the same conditions of hot carrier stress, the degradations of key electrical parameters are more obvious for the pre-irradiated one. In order to analyze the physical mechanism of the experimental phenomena, the wide channel device is tested too, we also analyze the phenomenon of the decrease of the substrate current of the wide channel device. From the contrasts of pre-irradiated and unirradiated devices, and narrow and wide channel device test results, we can obtain the following conclusions: SOI devices (especially the narrow channel device) with additional ionization irradiation field induced by ionizing radiation enhance the rate of injecting electrons into the silicon dioxide, and produce oxide trap charge and interface states, which leads to the fact that the channel carrier scattering becomes stronger, transfer characteristic curve of the device, output characteristic curve, transconductance curves and the related parameters of VT, GMmax, IDSAT degradation degree increase. So, when designing 130nm PD SOI NMOSFETs which are applied to the space environment, one should make a compromise between radiation resistance and HCI reliability.

Gas phase silanization for silicon nanowire sensors and other lab‐on‐a‐chip systems

AbstractDesigning a microfabrication process for lab‐on‐a‐chip systems can at times be challenging, and the need to integrate a chemical surface modification reaction into this process can limit the options. Therefore, a robust set‐up and protocol for the gas phase modification has been developed that can be variably integrated into microfabrication processes. The main improvement compared to similar methods is, besides easy and versatile sample handling, the integration of a continuous argon flow percolating through the liquid organosilane, and impinging directly the surface tobe modified. This measure reduces the argon consumption drastically compared to current reaction schemes, while keeping short reaction periods.Silicon substrates were modified using 3‐mercaptopropyltrimethoxysilane (MPTMS) and 3‐aminopropyltrimethoxysilane (APTMS), thoroughly studied for different reaction stages, and compared to surfaces modified via a common solvent‐based procedure from isopropanolic solution. Water contact angle measurements, infrared spectroscopy, X‐ray photoelectron spectroscopy, and atomic force microscopy verified the successful deposition of the alkylsilane. Additionally, silicon nanowires were assembled, exemplary for a lab‐on‐a‐chip system, in a liquid gate field‐effect‐transistor configuration, and electrically characterized. The devices showed the expected response to applied liquid gate potentials before and after the modification and exhibited characteristic changes in the transconductance curve. (© 2016 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Anomalous degradation behaviors under illuminated gate bias stress in a-Si:H thin film transistor

This study investigates the impact of gate bias stress with and without light illumination in a-Si:H thin film transistors. It has been observed that the I–V curve shifts toward the positive direction after negative and positive gate bias stress due to interface state creation at the gate dielectric. However, this study found that threshold voltages shift negatively and that the transconductance curve maxima are anomalously degraded under illuminated positive gate bias stress. In addition, threshold voltages shift positively under illuminated negative gate bias stress. These degradation behaviors can be ascribed to charge trapping in the passivation layer dominating degradation instability and are verified by a double gate a-Si:H device.