Power Consumption Of Transceiver Research Articles

Machine Learning for Self-Coherent Detection Short-Reach Optical Communications

Driven by emerging technologies such as the Internet of Things, 4K/8K video applications, virtual reality, and the metaverse, global internet protocol traffic has experienced an explosive growth in recent years. The surge in traffic imposes higher requirements for the data rate, spectral efficiency, cost, and power consumption of optical transceivers in short-reach optical networks, including data-center interconnects, passive optical networks, and 5G front-haul networks. Recently, a number of self-coherent detection (SCD) systems have been proposed and gained considerable attention due to their spectral efficiency and low cost. Compared with coherent detection, the narrow-linewidth and high-stable local oscillator can be saved at the receiver, significantly reducing the hardware complexity and cost of optical modules. At the same time, machine learning (ML) algorithms have demonstrated a remarkable performance in various types of optical communication applications, including channel equalization, constellation optimization, and optical performance monitoring. ML can also find its place in SCD systems in these scenarios. In this paper, we provide a comprehensive review of the recent progress in SCD systems designed for high-speed optical short- to medium-reach transmission links. We discuss the diverse applications and the future perspectives of ML for these SCD systems.

Time-domain low-complexity clock recovery for non-integer oversampled Nyquist signals with a small roll-off factor.

A clock recovery algorithm (CRA) suitable for non-integer oversampled Nyquist signals with a small roll-off factor (ROF) is appealing to short-reach high-speed inter-datacenter transmission systems which need to cut down the transceiver power consumption and cost by reducing the oversampling factor (OSF) and using cheap low-bandwidth components. However, due to the lack of a suitable timing phase error detector (TPED), CRAs proposed now fail for non-integer OSFs below two and small ROFs close to zero and are not hardware-efficient. To solve these problems, we propose a low-complexity TPED by modifying the time-domain quadratic signal and reselecting the synchronization spectral component. We demonstrate that the proposed TPED, in combination with a piece-wise parabolic (PWP) interpolator, can significantly improve the performance of feedback CRAs for non-integer oversampled Nyquist signals with a small ROF. Numerical simulations and experiments show that, based on the improved CRA, the receiver sensitivity penalty can keep below 0.5 dB when the OSF is reduced from 2 to 1.25 and the ROF is varied from 0.1 to 0.001 for 45 GBaud dual-polarization Nyquist 16QAM signals.

Design of high‐speed data transfer turbo code for body channel communication transceivers

SummaryIn this work, a digital differential transmitter based on low‐power wireless compensation transceiver for body channel communication (BCC) is proposed. Further, the proposed transceiver is composed of Touch Status Detection Unit (TSDU), Wireless Status Compensation Unit (WSCU), and a reconfigurable preamplifier. Initially, the human body channel environment for wireless communication is investigated based on properties from 1 to 100 MHz. Further, the turbo code‐based encoding scheme is used to encode the data before transferring the data on the transmitter side. Also, the proposed error‐correcting parallel turbo decoder using a modified step‐by‐step algorithm is presented. The turbo code‐based decoding scheme is used to recover the error‐free transmitted data at the receiver side. Results demonstrate that the proposed BCC transceiver is designed using 90 nm CMOS technology and it is observed that the proposed BCC transceiver has utilized an area of 600mm2. Also, the maximum data rate achieved by a proposed BCC transceiver was 100 Mbps, and the overall transceiver power consumption is 0.42 mW, and energy for communication is 0.02 nj/b.

Rate-Maximizing Zero-Forcing Hybrid Precoder for MU-MISO-OFDM

Hybrid precoders, consisting of an analog hardware-constrained part operating at radio frequency (RF) and a digital part operating at baseband, reduce the RF implementation complexity and power consumption of multi-antenna transceivers, at the expense of some rate loss compared to an all-digital precoder. The analog and digital parts of the hybrid precoder are commonly designed by performing a constrained matrix decomposition (MD) of the all-digital precoder, which aims to minimize the Euclidean distance between the matrices corresponding to the hybrid and the all-digital precoder. In contrast, in this contribution we determine the zero-forcing (ZF) hybrid precoder that directly maximizes the weighted sumrate of a MU-MISO-OFDM communication system, taking into account various hardware constraints on the analog part. The resulting maximum rate serves as a useful benchmark for comparison with other ZF hybrid precoders. In a multi-carrier massive MIMO scenario, the rate-maximizing ZF precoders show a considerable performance advantage over MD-type hybrid precoders, indicating that the latter precoders are far from optimum. This contribution also investigates the trade-off between performance and computational complexity. Because of the iterative nature of the rate-maximizing ZF hybrid precoders, their superior performance comes with a large computational complexity. When this complexity cannot be afforded, one should revert to the MD-type precoders, at the expense of a considerable performance penalty; among the MD-type precoders, the non-iterative ones have only a slightly worse performance but a significantly smaller computational complexity, in comparison with the iterative ones.

Multiple Tb/s Coherent Optical Transceivers for Short Reach Interconnect

This paper investigates coherent optical transceivers for short-reach interconnect, where a local oscillator laser is used to boost received optical signals for high receiver sensitivity. We review the state-of-the-art technologies and propose a miniature Mach-Zehnder modulator (mMZM) array with 3D silicon photonic-electronic integration to enable high-density, low-power multiple Tb/s coherent transceivers. For design optimization at transceiver level performances, we develop methodology and models to simulate PN junction and mMZM for high-efficiency high-speed modulation, which can be linked to system performances, including high-speed performances, receiver sensitivity, optical link budget, and coherent optical transceiver power consumption. With the optimized design and state-of-the-art technologies, we achieve highly integrated multiple Tb/s coherent transceivers with high density, high speed, and low power. Our simulation results show 3 pJ/bit for integrated driver/mMZM, 5 pJ/bit for integrated PIC/IC and 6.5 pJ/bit with transceiver optics for 6.4 Tb/s with 60 Gbaud 16QAM. Compared with conventional long phase shifter (PS) MZM (4 mm), mMZM with short PS (2.4 mm) only have an extra loss of ∼2 dB under 60 Gbaud 16QAM modulation with optimized designs. We study the scalability from 6.4 Tb/s to 12.8 Tb/s using 120 Gbaud 16QAM for intra-DC interconnect. The results show that further improvement for modulation efficiency, frequency response and laser output power are needed to enable the 12.8 Tb/s.

A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant Wake-Up Receivers and Low-Noise Primary Receivers.

Wake-up receivers (WuRX) present an opportunity to reduce average power consumption of IoT transceivers, however achieving sensitivity and interferer tolerance while providing wideband matching and sharing an antenna interface present a significant challenge for existing architectures. This paper presents a primary/WuRX which utilizes a quadrature hybrid coupler based N-Path mixer first architecture to simultaneously achieve low noise, wideband matching and a shared antenna interface. The passive-mixer first approach and a two-code modulated multi-tone signaling scheme provide interferer tolerance in the WuRX. The paper analyzes gain/power trade-offs in the proposed architecture in the context of noise impact with multi-tone WuRX signaling. The proposed architecture is implemented in 65 nm CMOS and occupies 2.25 mm 2. The primary RX achieves 3.8 dB NF and 0.75 dBm out-of-band P1dB with 440μW power consumption. The WuRX achieves -86 dBm sensitivity for 10kb/s data rate and up to -40 dB signal-to-interferer ratio (SIR) with 171μW power consumption.

Mesh Networking for Intermittently Powered Devices: Architecture and Challenges

Recent advances in low-power computing enable energy harvesting-powered devices, even in energy scarce conditions. This reduces the reliance on batteries in Internet of Things devices, reducing the cost and enabling new application domains. However, energy scarcity requires devices to operate intermittently, with minimal stored energy and where high-cost radio frequency (RF) communication dominates the power consumption, so transceivers are disabled most of the time. For deployment in challenging environments without high capability neighboring devices, a peer-to-peer topology for intermittently powered devices is required. To remove the requirement for high capability devices, we categorize four receiver types harnessing RF power transfer for a wake-up from other intermittently powered devices. This mesh networking of homogeneous nodes could enable applications where high power coordinators are undesirable or impossible. In this article, we identify the cross-layer challenges of mesh networking with intermittently powered devices and we describe the node receiver hardware required for peer-to-peer networking with intermittently powered devices. We conclude with a case study of transceiver power consumption in this context.

Long short-term memory neural network assisted peak to average power ratio reduction for underwater acoustic orthogonal frequency division multiplexing communication

The underwater acoustic wireless communication networks are generally formed by the different autonomous underwater acoustic vehicles, and transceivers are interconnected to the bottom of the ocean with battery deployed modems. Orthogonal frequency division multiplexing (OFDM) has become the most popular modulation technique in underwater acoustic communication due to its high data transmission and robustness over other modulation techniques. To maintain the operability of underwater acoustic communication networks, the power consumption of battery-operated transceivers becomes a vital necessity to be minimized. The OFDM technology has a major lack of peak to average power ratio (PAPR), resulting in more power consumption, creating non-linear distortion, and increasing the bit error rate (BER). To overcome this situation, we have contributed our research into three dimensions, firstly, we propose a machine learning-based underwater acoustic communication system through long short-term memory neural network (LSTM-NN). Secondly, the proposed LSTM-NN reduces the PAPR and makes the system reliable and efficient, turning into a better BER performance. Finally, the simulation and water tank experimental data results are executed which proves that the LSTM-NN is the best solution for mitigating the PAPR with non-linear distortion and complexity in the overall communication system

Wave Pipelined VLSI Architecture for a Viterbi Decoder Using Self Reset Logic with 0.65nm Technology

In 3G mobile terminals the Viterbi Decoder consumes approximately one third of the power consumption of a base band mobile transceiver. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. A low power Viterbi decoder is designed in circuit level using self reset logic and wave pipelining technique is implemented for high speed operation. The Viterbi decoder consists of four units like branch metric unit, add compare and select unit and the survivor path memory unit. All these units are designed using the self reset logic and wave pipelining, and simulated with its layout using MICROWIND TOOL in the 0.65nm technology, 1.8V Vdd and at a frequency of 10GHz. The simulation result shows that the power consumption is reduced by 70.55% and the speed of the circuit is increased by 45.83% compared to the Single Rail Domino Logic for constraint length of K =3 to 7.

Radio-frequency chain selection for energy and spectral efficiency maximization in hybrid beamforming under hardware imperfections

The next-generation wireless communications require reduced energy consumption, increased data rates and better signal coverage. The millimetre-wave frequency spectrum above 30 GHz can help fulfil the performance requirements of the next-generation mobile broadband systems. Multiple-input multiple-output technology can provide performance gains to help mitigate the increased path loss experienced at millimetre-wave frequencies compared with microwave bands. Emerging hybrid beamforming architectures can reduce the energy consumption and hardware complexity with the use of fewer radio-frequency (RF) chains. Energy efficiency is identified as a key fifth-generation metric and will have a major impact on the hybrid beamforming system design. In terms of transceiver power consumption, deactivating parts of the beamformer structure to reduce power typically leads to significant loss of spectral efficiency. Our aim is to achieve the highest energy efficiency for the millimetre-wave communications system while mitigating the resulting loss in spectral efficiency. To achieve this, we propose an optimal selection framework which activates specific RF chains that amplify the digitally beamformed signals with the analogue beamforming network. Practical precoding is considered by including the effects of user interference, noise and hardware impairments in the system modelling.

System Level Simulation of Energy-Detection Based UWB Receivers

The performance of a non-coherent UWB receiver with Binary pulse position modulation is simulated with MATLAB; taking into account the effect of non-linearity, noise, pulse shape and channel effects. This simulation examines the minimum requirements for LNA, AGC, squarer, and operational transconductance amplifier in analog front-end for sensor network application with 100Kb/s data rate and 10-3 BER. The linearity requirement in OTA is achieved using Gilbert cell OTA with the technique of multiple gated transistors. For sensor network applications, analog front-end modules must have 4dB NF (Noise figure), -12dBm IIP3, 50dB gain and -75dBm sensitivity for 100Kb/s data rates. The transceiver power consumption is assumed to be below 50mW. The performance of energy detection non-coherent receiver is simulated in Simulink of MATLAB, it shows that BER of Gaussian pulse is lower than doublet and 4th Gaussian pulse. By increasing the number of transmitted pulse per bit and IIP3, the performance of receiver is improved.

Supervised and Semi-Supervised Learning for MIMO Blind Detection With Low-Resolution ADCs

The use of low-resolution analog-to-digital converters (ADCs) is considered to be an effective technique to reduce the power consumption and hardware complexity of wireless transceivers. However, in systems with low-resolution ADCs, obtaining channel state information (CSI) is difficult due to significant distortions in the received signals. The primary motivation of this paper is to show that learning techniques can mitigate the impact of CSI unavailability. We study the blind detection problem in multiple-input-multiple-output (MIMO) systems with low-resolution ADCs using learning approaches. Two methods, which employ a sequence of pilot symbol vectors as the initial training data, are proposed. The first method exploits the use of a cyclic redundancy check (CRC) to obtain more training data, which helps improve the detection accuracy. The second method is based on the perspective that the to-be-decoded data can itself assist the learning process, so no further training information is required except the pilot sequence. For the case of 1-bit ADCs, we provide a performance analysis of the vector error rate for the proposed methods. Based on the analytical results, a criterion for designing transmitted signals is also presented. Simulation results show that the proposed methods outperform existing techniques and are also more robust.

Wideband Dual-Injection Path Self-Interference Cancellation Architecture for Full-Duplex Transceivers

A transceiver front end including a dual-injection path self-interference (SI) cancellation architecture is proposed for use in wideband full-duplex networks. The SI cancellation circuitry is implemented using: 1) one feedforward cancellation path containing a five-tap analog adaptive finite-impulse response (FIR) filter between the transmitter (TX) output and the receiver (RX) input; 2) a second baseband (BB) cancellation path containing a 14-tap low-frequency FIR filter with a point of injection at the RX BB output; 3) a phase noise cancellation method that suppresses the reciprocal mixing products associated with the downconversion in the BB cancellation path for the TX SI signal; and 4) an integrated noise cancelling power amplifier (PA). A prototype of 40-nm TSMC device was fabricated, which demonstrates more than 50-dB SI cancellation over 42-MHz bandwidth and a 10-dB attenuation of TX SI phase noise in the RX signal path. The two cancelling filters dissipate 11.5 mW, with a measured $P_{\mathrm {-1\,dB}}$ and IIP3 of 27/26.5 and 36/34.5 dBm, respectively. The RX noise figure is degraded by less than 1.55 dB, when both cancellers are enabled. The PA has a measured output of $P_{\mathrm {-1\,dB}}/P_{\mathrm {sat}}$ of 25.1/26.5 dBm, respectively. The total chip die area is 3.5 mm2 with an overall transceiver power consumption of 49 mW, excluding the integrated PA.

Evaluation of LoRa LPWAN Technology for Indoor Remote Health and Wellbeing Monitoring

Long lifetime of a wireless sensor/actuator node, low transceiver chip cost and large coverage area are the main characteristics of the low power wide area network (LPWAN) technologies. These targets correlate well with the requirements imposed by the health and wellbeing applications of the digital age. Therefore, LPWANs can found their niche among traditional short range technologies for wireless body area networks, such as ZigBee, Bluetooth and ultra wideband. To check this hypothesis, in this work we investigate the indoor performance with one of the LPWAN technologies, named LoRa, by the means of empirical measurements. The measurements were conducted using the commercially available devices in the main campus of the University of Oulu, Finland. In order to obtain the comprehensive picture, the experiments were executed for the sensor nodes operating with various physical layer settings, i.e., using the different spreading factors, bandwidths and transmit powers. The obtained results indicate that with the largest spreading factor of 12 and 14 dBm transmit power, the whole campus area (570 m North to South and over 320 m East to West) can be covered by a single base station. The average measured packet success delivery ratio for this case was 96.7%, even with no acknowledgements and retransmissions used. The campus was covered also with lower spreading factors with 2 dBm transmit power, but considerably more packets were lost. For example with spreading factor 8, 13.1% of the transmitted packets were lost. Aside of this, we have investigated the power consumption of the LoRa compliant transceiver with different physical layer settings. The experiments conducted using the specially designed module show that based on the settings used, the amount of energy for sending the same amount of data may differ up to 200-fold. This calls for efficient selection of the communication mode to be used by the energy restricted devices and emphasizes the importance of enabling adaptive data rate control.

An MR-FSK Transceiver Compliant to IEEE802.15.4g for Smart Metering Utility Applications: FPGA Implementation and ASIC Resource Estimation

This paper presents a fully integrated Multi-Rate and Multi-Regional Frequency Shift Keying (MR-FSK) transceiver compliant with IEEE 802.15.4g standard for Smart Metering Utility Networks (SUN). The total chip die area is 246.76 μm × 246.76 μm and the transceiver power consumption is 0.197319 mW. The architecture of this transceiver is depicted and resource estimations for ASIC and FPGA are presented, to assist the construction of SUN system and applications, such as advanced metering infrastructure (AMI).

A Novel Power-Saving Transmission Scheme for Multiple-Component-Carrier Cellular Systems

As mobile data traffic levels have increased exponentially, resulting in rising energy costs in recent years, the demand for and development of green communication technologies has resulted in various energy-saving designs for cellular systems. At the same time, recent technological advances have allowed multiple component carriers (CCs) to be simultaneously utilized in a base station (BS), a development that has made the energy consumption of BSs a matter of increasing concern. To help address this concern, herein we propose a novel scheme aimed at efficiently minimizing the power consumption of BS transceivers during transmission, while still ensuring good service quality and fairness for users. Specifically, the scheme utilizes the dynamic activation/deactivation of CCs during data transmission to increase power usage efficiency. To test its effectiveness, the proposed scheme was applied to a model consisting of a BS with orthogonal frequency division multiple access-based CCs in a downlink transmission environment. The results indicated that, given periods of relatively light traffic loads, the total power consumption of the proposed scheme is significantly lower than that of schemes in which all the CCs of a BS are constantly activated, suggesting the scheme’s potential for reducing both energy costs and carbon dioxide emissions.

A low power non-volatile LR-WPAN baseband processor with wake-up identification receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification (WUI) receiver for LR-WPAN transceiver. It consists of WUI receiver, main receiver, transmitter, non-volatile memory (NVM) and power management module. The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique, which increases the robustness and energy efficiency of receiver. The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver. The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode. The baseband processor is designed and verified on a FPGA board. The simulated power consumption of processor is 5.1μW for transmitting and 28.2μW for receiving. The WUI receiver technique reduces the average power consumption of transceiver remarkably. If the transceiver operates 30 seconds in every 15 minutes, the average power consumption of the transceiver can be reduced by two orders of magnitude. The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

Magnetic human body communication.

This paper presents a new human body communication (HBC) technique that employs magnetic resonance for data transfer in wireless body-area networks (BANs). Unlike electric field HBC (eHBC) links, which do not necessarily travel well through many biological tissues, the proposed magnetic HBC (mHBC) link easily travels through tissue, offering significantly reduced path loss and, as a result, reduced transceiver power consumption. In this paper the proposed mHBC concept is validated via finite element method simulations and measurements. It is demonstrated that path loss across the body under various postures varies from 10-20 dB, which is significantly lower than alternative BAN techniques.

Experimental Parametric Study of a Silicon Photonic Modulator Enabled 112-Gb/s PAM Transmission System With a DAC and ADC

A packaged silicon photonic traveling wave Mach-Zehnder modulator operating at 1310 nm is presented and studied. The modulator is a series push-pull device and requires a bias applied to the common n-doped region. Effects of varying the bias voltage on the modulator's V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">π</sub> bandwidth, and on chip-insertion loss are studied, and its impact on transmission performance are experimentally investigated for PAM-4 and PAM-8 formats at a throughput of 112 Gb/s, over varying distances of 0, 2, 10, and 20 km. Residual chromatic dispersion is shown to have no impact on performance up to 20 km. The PAM RF driving waveform is generated by an 8-bit digital-to-analog converter, while direct detection is done with a PIN+TIA followed by an 8-bit analog-to-digital converter. This IM/DD system utilizes digital signal processing with transmitter spectral compensation and receiver residual equalization. The performance impact for a varying number of transmitter precompensation taps and receiver equalization taps is studied, which has a direct impact on the transceiver's power consumption. Using PAM-4, a BER below the FEC limit is obtained for either combinations of (transmitter, receiver) tap lengths: (19,19), (7,27), or (35,7), allowing flexibility in power consumption distribution.

A fully integrated ieee IEEE 802.15.4g MR-FSK SoC soc for smart utility network applications

This paper presents a fully integrated multi-rate and multi-regional frequency shift keying (MR-FSK) system-on-chip (SoC) in 180-nm CMOS technology compliant with IEEE 802.15.4g standard for smart utility network (SUN). This SoC integrates all blocks including 800/900 MHz RF/Analog transceiver, digital modem, medium access controller (MAC) and security functions. The total SoC die area is 4.8 mm x 3.5 mm. The transceiver power consumption is 57 mW in receiving mode and 41 mW - 79 mW in transmitting mode, while the digital part consumes 19.5 mW. The implemented SoC exceeds the sensitivity requirements of IEEE 802.15.4g standard and is suitable for long-range and low-duty cycled SUN applications, such as advanced metering infrastructure (AMI).