Transceiver Front-end Research Articles

Collaborative Link-Aware Protocols for Energy-Efficient and QoS Wireless Body Area Networks Using Integrated Sensors

Integrated sensor systems are the promising solutions to the multiprobe design of biomedical sensors for energy efficient wireless body area networks (WBANs). To improve energy efficiency and communication quality-ofservice (QoS) of integrated sensor hubs, a cross-layered energyaware resource allocation (CLEAR) is proposed to exploit the characteristics of medium access control (MAC) and physical (PHY) layers of WBANs. The proposed MAC protocol applies a twin-token bucket model and real-time scheduling to the active superframe interleaving and beacon shifting techniques defined in the IEEE 802.15.6 standard. In addition, the proposed period transformation controlling task end-to-end delay improves the QoS while reducing packet collisions. The proposed PHY protocol is a hybrid of the transmit power control (TPC) and link adaption (LA) strategies, which coordinates the receiver and transmitter with link parameters including data rate, bit error ratio, receiver sensitivity, transmission power, modulation, etc. It adapts the link quality due to human postures or movements to meet the required QoS while minimizing the energy consumption of the transceiver front-end. Experimental results show that CLEAR outperforms existing methods in terms of packet delivery ratio, delay, bandwidth utilization, and energy consumption. In particular, CLEAR reduces average end-to-end delay by 21% as compared to existing methods, and saves an average of 18% of energy consumption over the TPC and LA-based methods at a power of -25 dBm while achieving a maximum 0.05 packet error ratio.

Integrated Systems-in-Package: Heterogeneous Integration of Millimeter-Wave Active Circuits and Passives in Fan-Out Wafer-Level Packaging Technologies

Recent advances in silicon semiconductor technology with transit and maximum oscillation frequencies above 300 GHz have enabled the integration of complex transceiver front ends operating in the millimeter-wave (mmW) regime for a variety of applications. Among these, the most prominent frequency ranges (and their associated applications) are currently the 60-GHz short-range communication frequency band [1]-[2] and E-band wireless back-haul solutions [3]-[4], as well as the 76-81-GHz band for automotive radar sensor realizations [5]-[6].

Novel Active Bandpass Switchplexer for RF Transceiver Front-End Applications

In this paper, the design of RF transceiver front-end using a novel multifunction microwave circuit is proposed. By designing one arm of the proposed active bandpass switchplexer as a bandpass power amplifier (PA) and the other arm as a single-to-balanced bandpass low-noise amplifier (LNA), the resulted multifunctional microwave filtering device thus effectively integrates the functions of single-pole-double-throw RF switch, bandpass filter, balun, PA, and LNA. In this way, all the function blocks between the antenna and up/down converters of a single-band time-division duplex transceiver front-end can be integrated into a single circuit. Compared to the previous works on multifunction microwave circuit designs, the proposed active bandpass switchplexer features the highest number of integrated functions. A printed circuit board-based design example of the proposed active bandpass switchplexer is presented to validate the proposed design concept and to demonstrate the performance achieved.

An Ultra-Low-Power Dual-Polarization Transceiver Front-End for 94-GHz Phased Arrays in 130-nm InP HBT

We present a fully integrated 94-GHz transceiver front-end in a 130-nm/1.1-THz $f_{{{\text {max}}}}$ InP HBT process. Low power is obtained through low-voltage design and high transistor gain. The IC is designed for multi-function, dual-polarization phased arrays. At 1.5-V collector bias, in dual-polarization simultaneous receiving mode, the IC has 21-dB gain, <9.3-dB noise figure, and consumes 39 mW, while in transmitting mode with time-duplexed vertical and horizontal outputs, the transceiver front-end achieves 5-dBm output power, 22-dB gain, and consumes 40 mW. At 1-V collector bias, in dual-polarization simultaneous receiving mode, the IC has 22.7-dB gain, <8.9-dB noise figure, and consumes 26 mW, while in transmitting mode, it has 22-dB gain and the saturated output power of 1.4 dBm with 29-mW power consumption.

Simulating the pre‐ and de‐emphasis of drive voltages of silicon‐based micro‐ring ring‐modulators

Integrated modulators are being intensely investigated and became potential candidates for the fundamental building blocks of next generation silicon-based front-end transceivers. Although suitable optical performance has been demonstrated in several works, theoretical models for the appropriate driving conditions of the micro-ring modulators are rarely explored. The carrier concentration fundamentally determines the refraction index of the pn junction of the modulator and to accelerate charge injection/extraction a pre- and de-emphasised driving voltage technique has been widely and successfully applied. Here we present a mathematical model where shooting amplitude and duration are considered with an optimised power consumption analysis. The model can be applied for both NRZ and RZ modulation formats.

A Comparative Analysis of CMUT Receiving Architectures for the Design Optimization of Integrated Transceiver Front Ends.

A formal comparison between fundamental RX amplifier configurations for capacitive micromachined ultrasonic transducers (CMUTs) is proposed in this paper. The impact on both RX and the pulse-echo frequency response and on the output SNR is thoroughly analyzed and discussed. It is shown that the resistive-feedback amplifier yields a bandpass RX frequency response, while both open-loop voltage and capacitive-feedback amplifiers exhibit a low-pass frequency response. For a given power dissipation, it is formally proved that a capacitive-feedback amplifier provides a remarkable SNR improvement against the commonly adopted resistive feedback stage, achieved at the expense of a reduced pulse-echo center frequency, making its use convenient in low-frequency and midfrequency ultrasound imaging applications. The advantage mostly comes from a much lower noise contributed by the active devices, especially with low- Q , broadband transducers. The results of the analysis are applied to the design of a CMUT front end in BIPOLAR-CMOS-DMOS Silicon-on-Insulator technology operating at 10-MHz center frequency. It comprises a low-power RX amplifier, a high-voltage Transmission/Reception switch, and a 100-V TX driver. Extensive electrical characterization, pulse-echo measurements, and imaging results are shown. Compared with previously reported CMUT front ends, this transceiver demonstrates the highest dynamic range and state-of-the-art noise performance with an RX amplifier power dissipation of 1 mW.

A 28 nm, 475 mW, and 0.4–1.7 GHz Embedded Transceiver Front-End Enabling High-Speed Data Streaming Within Home Cable Networks

A 28 nm CMOS software-defined transceiver (SDTRX) enabling high-speed data (HSD) streaming, including ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024-QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the-art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a digital-to-analog converter-based TX and a smart phase-locked loop system. It operates over 0.4–1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple transmitter (TX) to receiver (RX) loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia system-on-chip and is, to the authors’ knowledge, the first reported transceiver front-end to enable true HSD streaming within home cable networks.

Asymmetric Inductive Substrate bias RF SPDT Switch

In current technology world, wireless communication particularly in the front-end transceiver architecture has increased its functionality. The transmit/receive (T/R) switch has been developed with series-shunt topology integrated in 0.18µm standard CMOS technology operate on control voltage 1.8V for wireless application at 2.4 GHz frequency. The RF Single-Pole Double-Throw (SPDT) T/R switch is design using asymmetric inductive substrate bias technique. Switch design achieves low insertion loss (IL) and high isolation (ISO), linearity achieve by using a properly tuned LC tank. In the Transmit/Receive mode operation, the switch exhibits 1.1dB IL, 45.2dB isolation, >15dB return loss and 17.03dBm P1dB compression point, at 2.4 GHz frequency.

A 60 GHz CMOS Full-Duplex Transceiver and Link with Polarization-Based Antenna and RF Cancellation

This paper presents a fully integrated 60 GHz direct-conversion transceiver in 45 nm SOI CMOS for same-channel full-duplex (FD) wireless communication. FD operation is enabled by a novel polarization-based wideband reconfigurable self-interference cancellation (SIC) technique in the antenna domain. The antenna cancellation can be reconfigured from the IC to combat the variable SI scattering from the environment during in-field operation. A second RF cancellation path with $ > 30\;\text{dB}$ gain control and $ > 360^{\circ}$ phase control from the transmitter (TX) output to the LNA output further suppresses the residual SI to achieve the high levels of required SIC. With antenna and RF cancellation together, a total SI suppression of $ > 70\;\text{dB}$ is achieved over a cancellation bandwidth of 1 GHz and can be maintained in the presence of nearby reflectors. In conjunction with digital SIC (DSIC) implemented in MATLAB, a FD link is demonstrated over 0.7 m with a signal-to-interference-noise-and-distortion ratio (SINDR) of 7.2 dB. To the best of our knowledge, this work achieves the highest integration level among FD transceivers irrespective of the operation frequency and demonstrates the first fully integrated mm-wave FD transceiver front-end and link.

A Wideband Front-End Receiver Implementation on GPUs

Modern communication systems have frequency bands that are shared with multiple channels. A typical front-end transceiver is responsible for processing multiple channels simultaneously within the band. Although it is simpler to design a dedicated sub-transceiver for each channel, the overall cost of implementation is prohibitive. It is more desirable to design a single system that can process many channels at the same time. However, it is difficult to realize such a transceiver in wireless communication systems, since it needs to accommodate different standards, data rates, sampling rates, etc. In this paper, we address the challenges of flexible, cost-effective, multi-channel implementation of wideband receiver systems. In particular, we develop a novel implementation by applying graphics processing unit (GPU) technology to a wideband receiver that processes multiple channels at the same time, including channelization and arbitrary resampling. Our proposed new receiver architecture is flexible and reconfigurable via software, while providing high throughput and low latency.

Nonlinear Communication System With Harmonic Diversity

This paper presents the concept and demonstration of harmonic diversity for wireless communication, which makes use of multiple harmonic radio frequency (RF) channels with respect to the carrier frequency. Rather than frequency and space diversities widely used today to improve multipath fading, signal quality and spectral efficiency, the proposed scheme does not require multiple RF transceiver front-ends. The advantages of inherent RF device nonlinear characteristics are harnessed to produce and process harmonics within single transceiver. Even though distinct harmonic channels will exhibit different order of phase shifts, the analysis shows that such phase offsets can be compensated by adjusting the phase of local oscillator (LO) at receiver end. Extending the framework of the Shannon theorem, an $M$ -channel harmonic communication system is shown to reduce the minimum required signal-to-noise ratio (SNR) at the input of receiver by $M$ -times. In addition, this work indicates that the power consumption of transmitter can be significantly reduced up to 66% than the conventional ones. Through the analysis of channel capacity, the harmonic system is proved to outperform the single channel counterpart especially when SNR is low. To validate the correctness of the proposed concept, a series of experiments are carried out to emulate the developed theoretical models. For instance, a three-channel harmonic communication system is prototyped, involving certain RF harmonic components designed for demonstration. The retrieved signal strengths are examined with different phase setting of receiving LO, and various modulation techniques are applied for estimating the system performances. All measured results are in agreement with their simulated counterparts, thereby demonstrating the correctness and usefulness of the proposed theories and techniques for nonlinear communication systems of harmonic diversity.

RF Transceivers for Wireless Body Area Network Controllers

This paper focuses on the system and circuit level consideration of radio frequency front-end transceivers dedicated to WBAN controllers. We show how highly digitized transceivers employing sigma–delta modulators can achieve the frequency agility required by WBAN controllers. The paper compares the performance and highlights the pros and cons of I/Q transmitters and polar transmitters. For the receiver, different sigma–delta based RF receiver architectures are presented. These architectures are compared with more conventional architectures in terms of their suitability to WBAN controllers.

UHF RFID Localization Based on Evaluation of Backscattered Tag Signals

This paper introduces a 2-D position measurement system for passive ultra-high frequency (UHF) radio frequency identification (RFID) tags based on evaluation of backscattered transponder signals. The main application of the system is the localization of stationary objects tagged with RFID transponders. By combining phase and amplitude evaluation, the accuracy and the robustness of the position estimates are significantly improved compared with either approach alone. A multiple input multiple output system in which, sequentially, each frontend is configured to work as a transmitter while the remaining frontends serve as receivers is used to enable position estimation. For proof of concept, a local position measurement system demonstrator was built comprising conventional passive EPCglobal Class-1 Gen-2 UHF RFID tags, a commercial off-the-shelf RFID reader, eight transceiver frontends, baseband hardware, and signal processing. Measurements were carried out in an indoor office environment where the $3.5~{\mathrm{ m}} \times 2.5$ m measurement zone was surrounded by drywalls and concrete floor and ceiling. The experimental results showed accurate localization with a root-mean-square error of 0.020 m and a median error of 0.011 m. To determine the limits of the system, accuracy simulations were performed, which confirm the experimental results.

&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$W$&lt;/tex&gt;&lt;/formula&gt;-Band Dual-Polarization Phased-Array Transceiver Front-End in SiGe BiCMOS

This paper discusses the design and implementation of a 94-GHz phased-array transceiver front-end in SiGe BiCMOS that is capable of receiving concurrently in both vertical (V) and horizontal (H) polarizations and time-duplexed transmission in either polarization. The compact front-end is implemented in $\hbox{1.3 mm}\times \hbox{ 1.45 mm}$ of silicon area to ensure compatibility with a scalable phased-array tile approach with $\lambda/2~(\sim \hbox{1.6 mm})$ spacing between elements. Each transceiver front-end includes variable transmitter (TX) and receiver (RX) gain and 360 $^{\circ}$ variable phase shift in TX and RX. Co-integration of the transmit-receive (T/R) switch with the power amplifier (PA) and low-noise amplifier (LNA) matching network minimizes switch impact on RX noise figure (NF). A varactor-based passive reflection-type phase shifter (RTPS) is shared between the TX and RX to reduce area. Analysis of loss mechanisms in on-chip RTPS leads to a novel RTPS load that minimizes RTPS loss while ensuring that the amplitude variation across phase shift is $ . In RX mode, the front-end achieves 30-dB RX gain, bandwidth of 15 GHz (84–99 GHz) with $ 10-dB NF in the high-gain mode. In TX mode, the front-end achieves $> $ 2-dBm saturated output power and $> $ 0-dBm output-referred 1-dB compression point (OP1dB) in V and H polarizations (time-duplexed), 30-dB gain, and 8-GHz bandwidth (89–97 GHz). The 94-GHz phase shifters achieve full 360 $^{\circ}$ variable phase shift with 5-bit phase resolution (11.25 $^{\circ}$ resolution) and $ error and $ 1-dB rms gain error at 94 GHz. The front-end consumes 160 mW in RX mode for dual-polarization concurrent reception/phase-shifting and 116 mW in TX mode for time-duplexed V and H output in the $W$ -band.

UHF RFID Localization Based on Phase Evaluation of Passive Tag Arrays

This paper presents a 2-D localization system based on phase-of-arrival evaluation of passive ultrahigh frequency (UHF) radio frequency identification (RFID) transponders. To handle the ambiguity caused by phase evaluation, several tags are arranged to form a uniform linear array. A multiple input multiple output system, where sequentially each frontend is configured to work as transmitter, while the remaining frontends serve as receivers, is used to enable position estimation. For proof of concept, a local position measurement system demonstrator was built comprising conventional passive EPCglobal Class-1 Gen-2 UHF RFID tags, one commercial off-the-shelf RFID reader, several transceiver frontends, baseband hardware, and signal processing. Measurements were carried out in an indoor office environment, where the $3.5~{\rm m} \times 2.5$ m measurement zone was surrounded by drywalls and concrete floor and ceiling, and the experimental results showed robust and accurate localization with a root-mean-square deviation of 0.011 m and a maximum error of 0.032 m. These experimental results were confirmed by simulations, which were performed to determine the limits of the system accuracy.

An open source research platform for embedded visible light networking

Despite the growing interest in visible light communication, a reference networking platform based on commercial off-the-shelf components is not available yet. An open source platform would lower the barriers to entry of VLC network research and help the VLC community gain momentum. We introduce OpenVLC, an open source VLC research platform based on software-defined implementation. Built around a creditcard- sized embedded Linux platform with a simple opto-electronic transceiver front-end, OpenVLC offers a basic physical layer, a set of essential medium access primitives, as well as interoperability with Internet protocols. We investigate the performance of OpenVLC and show examples of how it can be used along with standard network diagnostics tools. Our software-defined implementation can currently reach throughput on the order of the basic rate of the IEEE 802.15.7 standard. We discuss several techniques that researchers and engineers could introduce to improve the performance of OpenVLC and envision several directions that can benefit from OpenVLC by adopting it as a reference platform.

A 240-GHz circularly polarized FMCW radar based on a SiGe transceiver with a lens-coupled on-chip antenna

A 240-GHz monostatic circular polarized SiGe frequency-modulated continuous wave radar system based on a transceiver chip with a single on-chip antenna is presented. The radar transceiver front-end is implemented in a low-cost 0.13 µm SiGe HBT technology version with cut-off frequencies fT/fmaxof 300/450 GHz. The transmit block comprises a wideband ×16 frequency multiplier chain, a three-stage PA, while the receive block consists of a low-noise amplifier, a fundamental quadrature down-conversion mixer, and a three-stage PA to drive the mixer. A differential branch-line coupler and a differential dual-polarized on-chip antenna are added on-chip to realize a fully integrated radar transceiver. All building blocks are implemented fully differential. The use of a single antenna in the circular polarized radar transceiver leads to compact size and high sensitivity. The measured peak-radiated power from the Si-lens equipped radar module is +11 dBm (equivalent isotropically radiated power) at 246 GHz and noise figure is 21 dB. The characterization bandwidth of the radar transceiver is 60 GHz around the center frequency of 240 GHz, and the simulated Tx-to-Rx leakage is below −20 dB from 230 to 260 GHz. After system calibration the resolution of the system to distinguish between two targets at different distance of 3.65 mm is achieved, which is only 21% above the theoretical limit.

A compact transmit/receive switch for 2.4 GHz reader-less active RFID tag transceiver

Radio frequency identification (RFID) is a ubiquitous identification technology nowadays. An on-chip high-performance transmit/receive (T/R) switch is designed and simulated in 0.13-μm CMOS technology for reader-less RFID tag. The switch utilizes only the transistor width and length (W/L) optimization, proper gate bias resistor and resistive body floating technique and therefore, exhibits 1 dB insertion loss, 31.5 dB isolation and 29.2 dBm 1-dB compression point (P1dB). Moreover, the switch dissipates only 786.7 nW power for 1.8/0 V control voltages and is capable of switching in 794 fs. Above all, as there is no inductor or capacitor used in the circuit, the size of the switch is 0.00208 mm2 only. This switch will be appropriate for reader-less RFID tag transceiver front-end as well as other wireless transceivers operated at 2.4 GHz band.

Process-Variation Tolerant Channel-Adaptive Virtually Zero-Margin Low-Power Wireless Receiver Systems

This paper presents a process-variation tolerant, continuously channel-adaptive wireless front-end architecture and related adaptation algorithms to allow a radio-frequency transceiver to function with minimum power at all channel conditions and manufacturing process corner. Current wireless transceiver front-ends are designed for worst case channel conditions and a limited degree of post manufacture tuning is performed to compensate for process variations. It is shown how the proposed architecture can result in significant power savings over current practice without compromising system-level bit-error rate (while keeping the end-user experience unaffected). In contrast to traditional wireless circuits with limited tunability, such a zero-margin design is achieved by close loop adaptation of the wireless front-end circuits to ensure that they only consume the minimum power and deliver just enough performance (and not any more) for any channel condition. The adaptation methodology is applied to a WLAN receiver design and hardware measurement data for an adaptive receiver is presented showing a > 3 × power improvement under best case channel conditions.

Radio Frequency Transceiver Architecture Energy Efficiency Analysis for Wireless Sensor Communications

Wireless Sensor Network (WSN) Communications technology enables the sensor nodes to observe, identify, understand and respond to changes in surrounding environment. Many of the communication devices for WSN have power constraints, due to their small size and the requirement to operate off small batteries for long periods of time. Thus energy efficiency is an important design criterion. Since energy consumption in the transceiver front ends is dominant, the focus is on reducing the energy consumption on the system level. In this research article the energy model for the alternating quadrature differential binary phase shift keying (AQ-DBPSK) modulation-based transceiver is developed and compared with the energy models for various transceiver architectures, popularly used in WSN nodes. Its suitability for energy efficient operations in WSN applications is investigated in this research article. Through theoretical analysis and simulated results, we discuss how to select the energy efficient transceiver front end for various WSN application scenarios.