Transactional Synchronization Extensions Research Articles

Enhancing transactional memory execution via dynamic binary translation

Transactional Synchronization Extensions (TSX) have been introduced for hardware transactional memory since the 4th generation Intel Core processors. TSX provides two software programming interfaces: Hardware Lock Elision (HLE) and Restricted Transactional Memory (RTM). HLE is easy to use and maintains backward compatibility with processors without TSX support, while RTM is more flexible and scalable. Previous researches have shown that critical sections protected by RTM with a well-designed retry mechanism as its fallback code path can often achieve better performance than HLE. More parallel programs may be programmed in HLE, however, using RTM may obtain greater performance. To embrace both productivity and high performance of parallel programs with TSX, we present a framework built on QEMU that can dynamically transform HLE instructions in an application binary to fragments of RTM codes with adaptive tuning on the fly. Compared to HLE execution, our prototype achieves 1.56 x speedup with 8 threads on average. Due to the scalability of RTM, the speedup will be more significant as the number of threads increases.

ParaTM: Transparent Embedding of Hardware Transactional Memory for Traditional Applications

As the many-core processors become more prevalent, the parallelism degree of applications is rapidly increasing. It is well known that multi-thread approaches are an effective solution to improve performance by exploiting multiple cores. However, the synchronization problem that occurs between multiple threads can limit the concurrency and scalability of applications. Hardware transactional memory (HTM) has been studied to simplify the synchronization problem, and Intel adopted transactional synchronization extensions (TSX) for its processors in the year 2012. TSX can dynamically decide and perform instructions as an atomic transaction. In this paper, we evaluate and analyze the performance of TSX. It is expected that the latest technology implementing HTM to cope with synchronization scalability will be a nice solution for handling the high degree of parallelism. We found two major reasons that cause performance degradation and propose a novel approach to address these more effectively based on our analysis. We also introduced a mechanism, named ParaTM, to transparently adopt TSX for existing lock-based applications. By using ParaTM, one can apply TSX features without modification of the code. From our evaluation using a micro-benchmark and real-world applications, we confirmed ParaTM is highly effective for transparency and performance. ParaTM achieved 1.75 $\times$ , 4.76 $\times$ , and 1.53 $\times$ better performance compared to the traditional lock mechanism for LevelDB, RocksDB, and Memcached, respectively.

Implementation of Intel Restricted Transactional Memory ISA Extension in Simics

Hardware transactional memory is finally becoming available in products from major vendors. Recently Intel announced that a set of transactional synchronization extensions (TSX) will be available in its next processor microarchitecture, codenamed Haswell. The benefits of software simulation of this technology will remain significant even after processors that support new instructions are available on the market. The reason for this is that a simulation often provides more flexibility during debugging and architecture exploration. In this paper we describe an implementation of Intel® restricted transactional memory (RTM) instructions, which are a part of the Intel® TSX, in the full system functional simulator Wind River® Simics. Our goal was to enable correct execution of these new instructions during all stages of operating system boot and user-level application execution and at the same time to keep the high simulation speed that Simics is able to demonstrate. This model is used to enable pre-silicon software development.