Implementation of Intel Restricted Transactional Memory ISA Extension in Simics

Abstract

Hardware transactional memory is finally becoming available in products from major vendors. Recently Intel announced that a set of transactional synchronization extensions (TSX) will be available in its next processor microarchitecture, codenamed Haswell. The benefits of software simulation of this technology will remain significant even after processors that support new instructions are available on the market. The reason for this is that a simulation often provides more flexibility during debugging and architecture exploration. In this paper we describe an implementation of Intel® restricted transactional memory (RTM) instructions, which are a part of the Intel® TSX, in the full system functional simulator Wind River® Simics. Our goal was to enable correct execution of these new instructions during all stages of operating system boot and user-level application execution and at the same time to keep the high simulation speed that Simics is able to demonstrate. This model is used to enable pre-silicon software development.