Transaction Level Model Research Articles

Simulation of discrete control systems with parallelism of behavior

Objectives. The problem of functional verification of control devices with respect to their design specification is considered. When solving the problems of implementing and testing of discrete systems, one has to deal with the presence of parallelism in the behavior of interacting control objects, which is also displayed in the assignment for designing control systems. The aim of the work is to develop a method for simulating descriptions of such systems, which allows their behavior testing dynamically on the area limited by their possible functioning.Methods. The paper considers a class of control systems with parallelism of the processes occurring in them, which permits linearization of their execution. To specify the behavior of such control systems, it is proposed to use the PRALU language of parallel control algorithms, which is based on Petri nets and which allows to order events occurring during the device operation. An object-oriented approach to simulation of the description of the control algorithm at the transaction level is proposed. For this purpose, a TLM (Transaction-Level Modeling) model has been developed for describing the devices with behavior parallelism in PRALU language. The transaction level model describes a system as a set of interacting processes that run in parallel and determine the behavior of the system over time.Results. The key concepts of the TLM model for simulating the descriptions of control algorithms in the PRALU language are defined: data structure, transactions, processes, and a barrier mechanism for synchronization of parallel processes. A method is proposed for transforming the description of an algorithm in the language into a TLM model, which is based on the representation of language operations as compositions of elementary operations that are performed sequentially. The set of these operations forms the basis for the algorithmic decomposition of a parallel algorithm in PRALU language into intermediate language program that is executed strictly sequentially. Translators of this program into the Verilog and C languages have been developed, the results of their compilation are simulators of the behavior of control system.Conclusion. The proposed simulation method can be used to create a test bench for functional verification of the circuit implementation of control devices with behavior parallelism. In this case, test sequences for verifying the circuit implementation can be generated dynamically – in the process of simulating the description of the algorithm in the PRALU language directly the control device or system, which include the control algorithm and the algorithms of controlled objects behavior.

Blockchain-based power trading system for microgrid

Direct trading between entities in the microgrid is the trend of micro-grid electricity trading. However, the lack of trust and endorsement among multiple entities in micro-grids makes it difficult to complete direct electricity transactions, which limits the green energy efficiency. To solve this problem, firstly, a blockchain-based microgrid power transaction level model and power transaction process management process are proposed. Secondly, an access interface between the microgrid smart terminal and the blockchain is designed to realize the connection between the blockchain and the underlying equipment. The system is implemented in an island microgrid, which realizes the peer-to-peer trading between power suppliers and users. The system builds a bridge among entities in microgrid and makes the power trading open, transparent and traceable.

Designing Electronic Systems Using SystemC and SystemC–AMS

Current trends in the design of electronic systems is the use of embedded systems based on systems on a chip (System-on-Chip (SoC)) or (VLSI SoC). The paper discusses the design features of electronic systems on a chip using the SystemC design and verification language. For the joint design and simulation of digital systems hardware and software, seven modeling levels are presented and discussed: executable specification, disabled functional model, temporary functional model, transaction-level model, behavioral hardware model, accurate hardware model, register transfer model. The SystemC design methodology with functional verification is presented, which reduces development time.The architecture of the SystemC language and its main components are shown. The expansion of SystemC–AMS for analog and mixed analog-digital signals and its use cases in the design of electronic systems are considered. Computing models are discussed: temporary data stream (TDF), linear signal stream (LSF) and electric linear networks (ELN). The architecture of the SystemC–AMS language standard is shown and examples of its application are given. It is shown that the design languages SystemC and SystemC–AMS are widely used by leading developers of computer-aided design systems for electronic devices.

Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

The simulation of interconnect architectures can be a time-consuming part of the design flow of on-chip multiprocessors. Accurate simulation of state-of-the art network-on-chip interconnects can take several hours for realistic application examples, and this process must be repeated for each design iteration because the interactions between design choices can greatly affect the overall throughput and latency performance of the system. This paper presents a series of network-on-chip transaction-level model (TLM) algorithms that provide a highly abstracted view of the process of data transmission in priority preemptive and non-preemptive networks-on-chip, which permit a major reduction in simulation event count. These simulation models are tested using two realistic application case studies and with synthetic traffic. Results presented demonstrate that these lightweight TLM simulation models can produce latency figures accurate to within mere flits for the majority of flows, and more than 93% accurate link dynamic power consumption modelling, while simulating 2.5 to 3 orders of magnitude faster when compared to a cycle-accurate model of the same interconnect.

대기사이클 고려 버스중재방식

The conventional bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in arbitrating the bus. The efficiency of bus usage can be determined by the selection of arbitration method. Fixed Priority, Round-Robin, TDMA and Lottery arbitration policies are studied in the conventional arbitration method where the bus transaction cycle, the wait cycle and the priority are primarily considered. In this paper, we propose the arbitration method that considers the wait cycle. Furthermore, we verify the bus transaction cycle and the wait cycle compared with the other arbitration methods through TLM(Transaction Level Model).

Automatic Generation of System Level Assertions from Transaction Level Models

We automatically generate assertions from Transaction Level Model (TLM) simulation traces. The generated assertions express design specifications in the form of linear temporal logic with quantitative temporal constraints [4]. We first generate the assertions without regard to the quantitative time constraints. They are mined in the form of frequent patterns in the simulation traces. We mine simulation traces using episode mining to identify frequent episodes comprising function calls and events. We then annotate the episodes with real time parameters to express quantitative time constraints among the function calls or events in the episode. When mining such TLM assertions, we employ symbolic execution to generalize the parameters and return values of function calls in the traces to help the mining engine generate high quality assertions. We have constructed a realistic AXI-based interconnection network platform that we demonstrate experimental results on. We show that our technique efficiently generates high quality performance and functional assertions on the AXI-based platform as well as a transaction level AMBA-based DMA controller. We demonstrate that episode mining is more scalable and able to generate a more compact set of high quality TLM assertions than previous efforts using sequential pattern mining. The number of generated assertions using episode mining can be reduced by up to 228 times, and the time interval between two events/function calls in each assertion is smaller than 50 time units.

Specification and encoding of transaction interaction properties

Transaction-level modeling is used in hardware design for describing designs at a higher level compared to the register-transfer level (RTL) (e.g. Cai and Gajski in CODES+ISSS '03: proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 19---24, 2003; Chen et al. in FMCAD '07: proceedings of the formal methods in computer aided design, pp. 53---61, 2007; Mahajan et al. in MEMOCODE '07: proceedings of the 5th IEEE/ACM international conference on formal methods and models for codesign, pp. 123---132, 2007; Swan in DAC '06: proceedings of the 43rd annual conference on design automation, pp. 90---92, 2006). Each transaction represents a unit of work, which is also a useful unit for design verification. In such models, there are many properties of interest which involve interactions between multiple transactions. Examples of this are ordering relationships in sequential processing and hazard checking in pipelined circuits. Writing such properties on the RTL design requires significant expertise in understanding the higher-level computation being done in a given RTL design and possible instrumentation of the RTL to express the property of interest. This is a barrier to the easy use of such properties in RTL designs. In this paper, we consider specification of interaction properties at the transaction-level and the subsequent encoding of the property and the transaction-level model as a finite-state system for model checking. We discuss how the encoded finite-state system can be automatically generated from the specification of the property and the transaction-level model, and illustrate this through simple examples.

A cycle-accurate transaction level SystemC model for a serial communication bus

This paper presents a transaction level SystemC model of an avionics mission system data bus that provides cycle-accurate simulation of the bus. The mission system is a complex distributed computer network consisting of a mission control computer, radars, an array of subsystems and sensors. The data bus plays a critical role in the system as it carries all the information between the system components. Therefore modelling the bus at an appropriate level of abstraction using appropriate technology is important for evaluation of the performance of both the bus and the entire system. While models based on traditional hardware description languages (HDL) provide cycle-accurate performance estimates they are very slow and have high code complexity. In order to enhance model performance this paper presents a transaction level model (TLM) utilizing the enhanced SystemC features and levels of abstraction. The TLM model incorporates a clock-based synchronisation strategy thereby providing cycle-accurate performance estimates like the HDL models. The developed model has been validated for various payloads and system sizes. Simulation results show that the proposed SystemC transaction level model is much more efficient than models developed using conventional hardware description languages.

Model Based Synthesis of Embedded Software

This paper presents software (SW) synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classif8cation of multicore embedded systems based on their platform architecture. We identify key design decisions and models that are required for embedded system synthesis. We present a model based design methodology that starts with an application model consisting of C processes communicating via abstract message passing channels. The application model is mapped to a platform net-list of SW and hardware (HW) cores, buses and buffers. A high speed Transaction Level Model (TLM) is generated to validate abstract communication between processes mapped to different cores. The TLM is further refined into a Pin-Cycle Accurate Model (PCAM) for board implementation. The PCAM includes C code for all the communication layers including routing, packeting, synchronization and bus transfer. The generated embedded SW provides a library of application level services to the C processes on individual SW cores. Therefore, the application developer does not need to write low level SW for board implementation. Synthesis results for multicore MP3 decoder and JPEG encoder designs, using ESE, show that the embedded SW is generated in order of seconds, compared to hours of manual coding. The quality of synthesized code is comparable to manually written code in terms of performance and code size. Over 3X productivity gain in overall multicore design is shown to result from automatic SW synthesis.

고속 SoC 검증을 위한 자동 가상 플랫폼 생성

In this paper, we propose an automatic generation method of transaction level(TL) model from algorithmic model to verify system specification fast and effectively using virtual platform. The TL virtual platform including structural properties such as timing, synchronization and real-time is one of the effective verification frameworks. However, whenever change system specification or HW/SW mapping, we must rebuild virtual platform and additional design/verification time is required. And the manual description is very time-consuming and error-prone process. To solve these problems, we build TL library which consists of basic components of virtual platform such as CPU, memory, timer. We developed a set of design/verification tools in order to generate a virtual platform automatically. Our tools generate a virtual platform which consists of embedded real-time operating system (RTOS) and hardware components from an algorithmic modeling. And for communication between HW and SW, memory map and device drivers are generated. The effectiveness of our proposed framework has been successfully verified with a Joint Photographic Expert Group (JPEG) and H.264 algorithm. We claim that our approach enables us to generate an application specific virtual platform faster than manual designs. Also, we can refine an initial platform incrementally to find a better HW/SW mapping. Furthermore, application software can be concurrently designed and optimized as well as RTOS by the generated virtual platform

Static Analysis of Transaction-Level Communication Models

We propose a methodology for the early estimation of communication implementation choice effects, starting from an abstract transaction-level system model (TLM). The reference version of the TLM considered is the Open SystemC initiative library. The methodology is based on the computation of metrics that abstract useful information from the initial system model. The metrics are precisely defined upon a general formal model of transaction-level system descriptions. A set of design problems of relevant interest, such as shared communication resource assignment, pipelining partitioning, bandwidth, and latency constraint estimation, is considered to show some potential applications of the metrics proposed.

The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model

Design technology is expected to rise to electronic system-level (ESL). This necessitates new techniques and tools for synthesizing ESL designs and for verifying them before and after ESL synthesis. A promising verification strategy for future very complex designs is to initially verify the design at the highest level of abstraction, and then check the equivalence of the lower level automatically generated models against that initial golden model. We present one such approach to simulation-based functional verification implemented in our ESL design methodology called ODYSSEY. Our ESL synthesis tool generates a transaction-level model (TLM) at TLM level 2 (i.e., design with partial timing) that corresponds to the input ESL design (which is at TLM level 3; i.e., sole functionality without timing). Both the ESL design and its generated TLM model can be simulated on a host machine with corresponding input stimuli to establish their functional equivalence. The TLM is in SystemC, and hence executable, and also models both hardware and software components in C++ to achieve higher simulation speed. We introduce an implementation of a TLM level 2 model that is tailored to our ESL design methodology and apply our approach to a number of benchmarks to evaluate the TLM simulation performance. Experimental results show that the approach suits early validation of the ESL synthesis process since its simulation performance is more than 4 orders of magnitude higher than simulations at lower levels and it is generated early in the design cycle. Also the co-simulation overhead – compared to simulating the original ESL design in C++ – depends on the partitioning quality in terms of communication to computation ratio.

Graph based test case generation for TLM functional verification

Describing complex systems at a high level of abstraction provides designers with the possibility of exploring multiple SoC design architectures before committing to the low level-details of a complete implementation. Transaction level modeling understandably expedites the design simulation and verification. During the verification process, generating good test cases plays a significant role in determining the quality of the design. Inadequate test cases may cause bugs to remain. In this paper, first, in order to generate test cases for a TL model, we present a Control-Transaction Graph (CTG) which describes the behavior of a TL Model. A Control Graph is a control flow graph of a module in the design and transactions represent the interactions such as synchronization between modules. Second, we define dependent paths ( DePaths) on the CTG as test cases for a transaction level model, which can find communication errors in simulation. We also give coverage metrics for a TL model to measure the quality of the generated test cases. Finally, we apply our method on the SystemC model of AMBA–AHB bus and JPEG encoder and generate test cases based on the CTG of these models.

Automatic generation of embedded communication SW for heterogeneous MPSoC platforms

This paper addresses the problem of long design cycle of MPSoCs communication SW with automatic synthesis. The tool we propose takes as input a transaction level model (TLM) of MPSoC communication and outputs pin and cycle-accurate (PCA) bus drivers that can be linked to the synthesizable PCA model (PCAM). The TL communication is simple since TLM channels abstract away protocol details. PCAM communication, in turn, includes explicit definitions for each signal and pin. However, in most cases the TLMs are not suitable for implementation since they do not reflect the MPSoC platform. Usually the designers simulate (fast) TLMs, then manually implement PCA communication. Our communication SW synthesis transforms TL send and receive functions into platform specific PCAM bus drivers which can be automatically downloaded to the FPGA board. The presented results demonstrate the significant productivity gain achieved with our tool, with no great cost to either code size or system performance.

SPRINT: A Tool to Generate Concurrent Transaction-Level Models from Sequential Code

A high-level concurrent model such as a SystemC transaction-level model can provide early feedback during the exploration of implementation alternatives for state-of-the-art signal processing applications like video codecs on a multiprocessor platform. However, the creation of such a model starting from sequential code is a time-consuming and error-prone task. It is typically done only once, if at all, for a given design. This lack of exploration of the design space often leads to a suboptimal implementation. To support our systematic C-based design flow, we have developed a tool to generate a concurrent SystemC transaction-level model for user-selected task boundaries. Using this tool, different parallelization alternatives have been evaluated during the design of an MPEG-4 simple profile encoder and an embedded zero-tree coder. Generation plus evaluation of an alternative was possible in less than six minutes. This is fast enough to allow extensive exploration of the design space.

Verification of System Level Model Transformations

This paper presents Model Algebra (MA), a formalism for representing SoC designs at system level. We define the objects and composition rules of MA and show how system level models can be represented as expressions in this formalism. The formalism is applied to a system level design methodology, where design decisions are used to gradually transform the functional specification model of the system to a transaction level model with components and communication structure. Each transformation is represented as a manipulation of a model algebraic expression, and proven for correctness using the laws of model algebra. These laws are based on the well defined execution semantics and notion of functional equivalence for MA models. Our approach promises significant savings in the verification of system level models because only the first model needs to be verified using conventional techniques. All transformations of this model, derived using MA laws, are proven to be functionally equivalent.

Implementation of transaction level AMBA bus models using systemC

This paper deals with how to implement AMBA bus transaction level modeling in SystemC. There are two main techniques used in the whole modeling process, which consist of starting the platform modeling at the transaction level and using the uniformed modeling language— System C. According to the concepts of interface, port and hierarchical channel introduced in SystemC 2.0, the system of master-channel (AMBA bus) slave is created as the architecture of the AMBA bus transaction level model, which can make it more extendable. The port and interface classes of the model that are prone to program are defined in accordance with the SoC hierarchical design methodology. In addition, method calls, not signal communication, are used between different modules in the model, so the higher-level abstraction is achieved and the simulation performance is improved. The AMBA bus transaction level model is analyzed and certified by simulation experiment, and proved to be completely compliant to the AMBA specification 2.0.

A Bayesian paradigm for designing intrusion detection systems

This article describes a model based approach to designing network intrusion detection systems. The article considers general methods applicable to many different types of networks, using specific algorithms as examples. The central theme is that latent variable hierarchical models constructed using Bayesian methods lead to coherent systems that can handle the complex distributions involved with network traffic. Bayes’ rule provides a means of combining competing intrusion detection methods such as anomaly detection and pattern recognition. Bayesian methods present evidence of intrusion as probabilities, which are easy for human fraud investigators to interpret. Hierarchical models allow transactions to communicate information about possible intrusions across time and accounts. These hierarchical models contain a transaction level model describing how well individual network transactions fit user and intruder profiles, an account level model parameterizing bursts associated with network intrusion, and a network-level model that adjusts account level model parameters when an intrusion on one or more account is suspected.