A cycle-accurate transaction level SystemC model for a serial communication bus

Abstract

This paper presents a transaction level SystemC model of an avionics mission system data bus that provides cycle-accurate simulation of the bus. The mission system is a complex distributed computer network consisting of a mission control computer, radars, an array of subsystems and sensors. The data bus plays a critical role in the system as it carries all the information between the system components. Therefore modelling the bus at an appropriate level of abstraction using appropriate technology is important for evaluation of the performance of both the bus and the entire system. While models based on traditional hardware description languages (HDL) provide cycle-accurate performance estimates they are very slow and have high code complexity. In order to enhance model performance this paper presents a transaction level model (TLM) utilizing the enhanced SystemC features and levels of abstraction. The TLM model incorporates a clock-based synchronisation strategy thereby providing cycle-accurate performance estimates like the HDL models. The developed model has been validated for various payloads and system sizes. Simulation results show that the proposed SystemC transaction level model is much more efficient than models developed using conventional hardware description languages.