Traditional Register Transfer Level Research Articles

Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration

One of the biggest advantages of C-based very large scale integration design over traditional register transfer level is its ability to automatically generate architectures with different area versus performance characteristics without the need of modifying the original behavioral description. Different knobs can be explored to obtain the dominating tradeoff curve (Pareto-front). So far previous works have only focused on exploring one set of knobs or combining all of them together without considering the underlying implications of each of these knobs. This paper presents the first method that accelerates the design space exploration (DSE) by first classifying these knobs and exploring them sequentially, thus reducing the design space to be explored considerably. In particular: 1) local synthesis directives in the form of pragmas inserted directly at the source code and 2) functional units (FUs) number and type. Second, we propose a probabilistic method to further accelerate the DSE by computing the probability of each micro-architecture generated after the pragma exploration stage, to lead to new dominating designs and in turn exploring only those with the highest probabilities. One additional contribution is that the explorer for both knobs are implemented using novel heuristics. The pragma based explorer is based on ant colony optimization, while the FU explorer explores the number and type of FUs in order to further maximize the total amount of resource sharing that can be extracted. Experimental results show that our proposed method finds Pareto-fronts of similar quality than an exploration method optimized for quality of their results, while accelerating the DSE by an average of $12.2 {\times }$ .

SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration

To assist the system architects with fast exploration and performance evaluation of the reconfigurable software/hardware architectures, this paper presents a system-level simulator, named after SimRPU, for the reconfigurable processing unit (RPU), which is the major computing engine in reconfigurable processor. The proposed simulator consists of a simulation kernel, a software compiler, a system profiler providing performance, area and power information for the desired architectures, and a system debugger supporting inspecting and modification of the internal state of the RPU. Object-oriented hierarchical and parameterized architecture modeling techniques are proposed to satisfy the requirements for a fast and comprehensive evaluation. Cycle-accurate simulation mechanisms are developed to improve the accuracy of the profiled performance data. Compared with the traditional register transfer level (RTL) based simulation scheme, the proposed simulator could achieve an average speedup of 18.5× with only 3.5% reduction on performance estimation accuracy. One reconfigurable processor targeted at high-definition multimedia decoding applications (such as H.264, MPEG2, AVS, etc.) is implemented with Taiwan Semiconductor Manufacturing Company 65-nm process using the proposed exploration and design flow. The measured results show that the implemented architecture has obvious advantages in terms of both performance and power consumption than the reference designs in multimedia decoding applications.

Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools

In this study we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using high-level synthesis (HLS) tools. These modern FPGA design tools accept C/C++ descriptions as input specifications, and automatically generate a register transfer level (RTL) description for FPGA implementation using traditional FPGA implementation tools. We have used AutoESL's AutoPilot HLS tool to implement this demanding algorithm on a Virtex-5 running at a clock frequency of 225 MHz. The obtained results show that these modern HLS tools produce Quality of Results competitive to the ones obtained using a traditional RTL design approach, while significantly abstracting the designer from the low-level FPGA implementation details.