Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration

Abstract

One of the biggest advantages of C-based very large scale integration design over traditional register transfer level is its ability to automatically generate architectures with different area versus performance characteristics without the need of modifying the original behavioral description. Different knobs can be explored to obtain the dominating tradeoff curve (Pareto-front). So far previous works have only focused on exploring one set of knobs or combining all of them together without considering the underlying implications of each of these knobs. This paper presents the first method that accelerates the design space exploration (DSE) by first classifying these knobs and exploring them sequentially, thus reducing the design space to be explored considerably. In particular: 1) local synthesis directives in the form of pragmas inserted directly at the source code and 2) functional units (FUs) number and type. Second, we propose a probabilistic method to further accelerate the DSE by computing the probability of each micro-architecture generated after the pragma exploration stage, to lead to new dominating designs and in turn exploring only those with the highest probabilities. One additional contribution is that the explorer for both knobs are implemented using novel heuristics. The pragma based explorer is based on ant colony optimization, while the FU explorer explores the number and type of FUs in order to further maximize the total amount of resource sharing that can be extracted. Experimental results show that our proposed method finds Pareto-fronts of similar quality than an exploration method optimized for quality of their results, while accelerating the DSE by an average of $12.2 {\times }$ .