Traditional Multi-core Processors Research Articles

Architecturally truly diverse systems: A review

The pairing of traditional multicore processors with accelerators of various forms (e.g., graphics engines, reconfigurable logic) can be referred to generally as architecturally diverse systems. Our interest in this work is truly diverse systems, in which more than one accelerator is used in the execution of an application. These systems have the potential for substantial performance gains relative to multicores alone; however, they pose significant difficulties when it comes to application development.In spite of these difficulties, the use of accelerators in high performance computation, generally, has grown substantially over the past decade. This is primarily due to a pair of forces. First, with the demise of Dennard scaling, power has become a substantial limiting factor in systems development, pushing computations to be more power efficient (a strength of many accelerators). Second, the application development environments for accelerators have improved substantially in recent years.We review the use of multiple, distinct accelerators deployed in a individual system or, more to the point, used concurrently within an individual application. We give a history of architecturally diverse systems that use multiple accelerators, discuss the motivations for diversity in accelerators, and describe the approaches that both system designers and application developers have used to put accelerators to beneficial use.

A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity

With the skyrocketing advances of process technology, the increased need to process huge amount of data, and the pivotal need for power efficiency, the usage of Graphics Processing Units (GPUs) for General Purpose Computing becomes a trend and natural. GPUs have high computational power and excellent performance per watt, for data parallel applications, relative to traditional multicore processors. GPUs appear as discrete or embedded with Central Processing Units (CPUs), leading to a scheme of heterogeneous computing. Heterogeneous computing brings as many challenges as it brings opportunities. To get the most of such systems, we need to guarantee high GPU utilization, deal with irregular control flow of some workloads, and struggle with far-friendly-programming models. The aim of this paper is to provide a survey about GPUs from two perspectives: (1) architectural advances to improve performance and programmability and (2) advances to enhance CPU–GPU integration in heterogeneous systems. This will help researchers see the opportunities and challenges of using GPUs for general purpose computing, especially in the era of big data and the continuous need of high-performance computing.

Quick Answer for Big Data in Sharing Economy: Innovative Computer Architecture Design Facilitating Optimal Service-Demand Matching

In sharing economy, people offer idle social resources to others in a sharing manner. Through community-based online platforms, the people offering services can earn commission while others can enjoy a better life via renting social resources. Consequently, the value-in-use of services is expectedly strengthened within the unit time, although the total amount of social resources remains constant. Influenced by sharing economy, some famous companies have developed intelligent systems to analyze the most appropriate coincidence between citizens’ idle supply and renting demand from numerous data sets. However, the big data analysis of the optimal service-demand matching usually runs on the traditional multiprocessors equipped in intelligent systems, so-called “system-on-chip.” In this paper, we design a novel computer architecture—the accelerator based on optical network-on-chip (ONoC)—to further speed up the matching between citizens’ offer and demand in sharing economy. Our ONoC-based accelerator is able to quickly calculate the optimal service-demand matching by processing computation tasks on parallel cores, i.e., task-core mapping. In addition, to improve the accelerator reliability, the assorted task-core mapping algorithm is also designed. The extensive simulation results based on real trace file demonstrate the effectiveness of our system and algorithm. Note to Practitioners —Sharing economy is of great importance for realizing green consumption and sustainable development in our human society. Sharing economy enterprise calls for intelligent system design for service-demand matching in the current big data era. In this paper, we design the accelerator based on ONoC to further speed up the matching between citizens’ offer and demand in sharing economy. By processing computation tasks on parallel cores using our algorithm, the task-core mapping can be performed with high speed and reliability. The simulation results—based on the trace file of Amazon Mechanical Turk—can well guide the practitioners to design a more clever and reliable product by quickly calculating the optimal service-demand matching.

Threads Distribution Effects on Graphics Processing Units Neutron Sensitivity

Graphic Processing Units offer the possibility of executing several threads in parallel, providing the user with higher throughput with respect to traditional multi-core processors. However, the additional resources required to schedule and handle the parallel processes may have the countermeasure of making GPUs more prone to be corrupted by neutrons. The reported experimental results prove that un-optimized thread distribution may exacerbate the device output error rate. As demonstrated, increasing the parallel algorithm block size minimizes the GPU neutron-induced output error rate. The GPU parallelism management is then analyzed as a method to increase reliability.

Particle-in-Cell algorithms for emerging computer architectures

We have designed Particle-in-Cell algorithms for emerging architectures. These algorithms share a common approach, using fine-grained tiles, but different implementations depending on the architecture. On the GPU, there were two different implementations, one with atomic operations and one with no data collisions, using CUDA C and Fortran. Speedups up to about 50 compared to a single core of the Intel i7 processor have been achieved. There was also an implementation for traditional multi-core processors using OpenMP which achieved high parallel efficiency. We believe that this approach should work for other emerging designs such as Intel Phi coprocessor from the Intel MIC architecture.

High level performance metrics for FPGA-based multiprocessor systems

New high performance architectures combining high and low level design techniques are widely used today, and FPGA platforms offer excellent solutions for this kind of system. There are a lot of multiprocessor systems implemented on FPGAs but the performance metrics usually considered with the traditional multiprocessors have not been adapted for systems on chip yet. For these high performance systems the classic hardware metrics, such as area, cost and minimum period, are still used; but sometimes they do not provide enough information to guide users and designers in their decisions. In this paper, new definitions for high level performance metrics such as efficiency, scalability and robustness are proposed to overcome these limitations with FPGA-based multiprocessor systems.

A performance-based parallel loop scheduling on grid environments

The effectiveness of loop self-scheduling schemes has been shown on traditional multiprocessors in the past and computing clusters in the recent years. However, parallel loop scheduling has not been widely applied to computing grids, which are characterized by heterogeneous resources and dynamic environments. In this paper, a performance-based approach, taking the two characteristics above into consideration, is proposed to schedule parallel loop iterations on grid environments. Furthermore, we use a parameter, SWR, to estimate the proportion of the workload which can be scheduled statically, thus alleviating the effect of irregular workloads. Experimental results on a grid testbed show that the proposed approach can reduce the completion time for applications with regular or irregular workloads. Consequently, we claim that parallel loop scheduling can benefit applications on grid environments.

The Jrpm system for dynamically parallelizing Java programs

We describe the Java runtime parallelizing machine (Jrpm), a complete system for parallelizing sequential programs automatically. Jrpm is based on a chip multiprocessor (CMP) with thread-level speculation (TLS) support. CMPs have low sharing and communication costs relative to traditional multiprocessors, and thread-level speculation (TLS) simplifies program parallelization by allowing us to parallelize optimistically without violating correct sequential program behavior. Using a Java virtual machine with dynamic compilation support coupled with a hardware profiler, speculative buffer requirements and inter-thread dependencies of prospective speculative thread loops (STLs) are analyzed in real-time to identify the best loops to parallelize. Once sufficient data has been collected to make a reasonable decision, selected loops are dynamically recompiled to run in parallel.Experimental results demonstrate that Jrpm can exploit thread-level parallelism with minimal effort from the programmer. On four processors, we achieved speedups of 3 to 4 for floating point applications, 2 to 3 on multimedia applications, and between 1.5 and 2.5 on integer applications. Performance was achieved by automatic selection of thread decompositions by the hardware profiler, intra-procedural optimizations on code compiled dynamically into speculative threads, and some minor programmer transformations for exposing parallelism that cannot be performed automatically.

Disk caching with an optical ring

We propose a simple extension to the optical network of a scalable multiprocessor that optimizes page swap outs. More specifically, we propose to extend the network with an optical ring that not only transfers swapped-out pages between the local memories and the disks of the multiprocessor but also acts as a systemwide write cache for these pages. This extended optical network confers several performance benefits: It provides a staging area where swapped-out pages can reside until the disk is free, it increases the possibility of combining several writes to disk, and it acts as a victim cache for pages that are swapped out and subsequently accessed by the same or a different processor. To evaluate the extent to which these benefits affect performance, we use detailed execution-driven simulations of several out-of-core parallel applications that run on an eight-node scalable multiprocessor. Our results demonstrate that our optical ring provides consistent performance improvements that derive mostly from faster page swap outs and victim caching. To show that our optical ring can also be applied successfully to traditional multiprocessors in which processors are interconnected with electronic networks, we evaluate its benefits for a mesh-connected multiprocessor. This latter evaluation shows that our optical ring improves performance for a traditional multiprocessor by roughly the same amount as it does for an optically interconnected multiprocessor. On the basis of these results and our parameter-space study our main conclusion is that our optical ring is highly efficient under several architectural assumptions and for most out-of-core parallel applications. Even though our study focuses on optimizing page swap outs, we believe that caching data with an optical ring can be beneficial for other types of disk-write traffic as well.