Traditional Complementary Metal Oxide Semiconductor Research Articles

Design of SRAM cell using an optimized D-latch in quantum-dot cellular automata (QCA) technology

A newer nanoscale technology called quantum-dot cellular automata (QCA) has been used by researchers to design digital circuits in place of the more traditional complementary metal–oxide semiconductor (CMOS) technology. This recent development in the technology change is due to the problems faced by CMOS technology in terms of power consumption and physical limitations. The advantages of QCA technology over CMOS technology are high density, low power consumption, high-speed operation, and less footprint area. This research provides a novel circuit for D-latch and static random access memory (SRAM) cells based on QCA technology. Initially, a D-latch circuit is proposed with a layout area of 0.01 μm2, a 0.5 clock cycle delay (latency), and a cell count of 18 QCA cells. Furthermore, an SRAM cell is proposed using the same D-latch circuit, which uses cell counts of 26 QCA cells and contributes to a layout area of 0.02 μm2 with a 0.75 clock cycle delay (latency). It is observed that our proposed circuits have a smaller layout area, fewer QCA cell counts, and a lower clock cycle delay (latency) than existing circuits.

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

Exploring statistical approaches for accessing the reliability of Y2O3-based memristive devices

Memristive devices have emerged as promising alternatives to traditional complementary metal-oxide semiconductor (CMOS)-based circuits in the field of neuromorphic systems. These two-terminal electronic devices, known for their non-volatile memory properties, can emulate synaptic behavior within artificial neural networks, offering remarkable advantages, including scalability, energy efficiency, rapid operation, compact size, and ease of fabrication. They hold the potential to serve as fundamental components for artificial neurons, revolutionizing neuromorphic computing systems by closely mimicking biological neurons. However, the integration of resistive random-access memory (RRAM) into commercial production faces challenges due to substantial variations in resistive switching (RS) parameters, which include cycle-to-cycle (C2C) and device-to-device (D2D) fluctuations. These variations are rooted in the stochastic nature of RS, linked to physical mechanisms like diffusion and redox reactions. Nonetheless, limitations exist in the current analytical approaches, emphasizing the need for more standardized tools to assess memristive device reliability consistently. Weibull distribution is widely used to analyze RRAM variability and many further studies are based on it. However, this distribution may not work well for some memristive devices. In such cases, one can use other statistical distributions available in the literature. In the present work, statistical distributions, namely Weibull, Exponential, Log-Normal, Gamma, and Logistic distributions, are employed to scrutinize memristive devices device parameters, shedding light on their performance and reliability. Also, analytical methods namely maximum likelihood estimates for parameter estimation and Kolmogorov-Smirnov test for assessing goodness of fit of the distributions are used. This study aims to provide an approach with a deeper understanding of memristive device parameters and analysis techniques.

Novel energy efficient RND inverter using quantum dot cellular automata in nanotechnology

Quantum-Dot Cellular Automata (QCA) is a promising technology for designing high-performance and efficient logic circuits, surpassing traditional Complementary Metal Oxide Semiconductor approaches. In today’s digital era, the demand for digital circuits with high speed, device density, and energy efficiency is paramount. This paper focuses on the innovative Rotated Normal Cells with Displacement (RND) inverter model, employing normal and rotated cells with a 10 nm displacement through a cell interactive method. Digital circuits designed using the RND inverter exhibit superior performance compared to existing designs. The proposed RND inverter gate utilizes only four QCA cells, occupying a total area of 4525.55 nm2. With a total energy dissipation of 0.508 meV and an average energy dissipation per cycle of 0.0462 meV, it achieves a polarization of 9.77. The novel RND inverter demonstrates a 44% improvement in cell area and a 63% reduction in total area compared to current designs, offering enhanced energy efficiency with 0.26 improved polarization. The RND inverter and the digital circuits facilitate finding applications in efficiently constructing various components within Quantum Computers. Beyond quantum computing, the RND inverter proves applicable in designing Nano-sized electronic gadgets and temperature-controlled circuits, showcasing its versatility across diverse technological applications.

A Comparative Analysis of VS-CNTFET and CMOS Based Inverter Circuit

This abstract delves into the comparative exploration between Carbon Nanotube Field Effect Transistors (CNTFETs) and traditional CMOS (Complementary Metal-Oxide-Semiconductor) transistors, with a specific emphasis on digital inverter circuits. Utilizing carbon nanotubes derived from the graphene allotrope, CNTFETs are introduced as a technological advancement, providing advantages such as reduced size and lower power consumption. The investigation centres on the evaluation of the Stanford model, particularly focusing on the Virtual Source Carbon Nanotube Field Effect Transistor. This specific model showcases superior performance, compact dimensions, and decreased power requirements when contrasted with silicon-based MOSFETs. The analytical process involves subjecting virtual source CNTFET inverter circuits and MOSFET-based circuits to testing via the Symica software tool, encompassing the examination of transient response, voltage transfer characteristics, and steady-state power consumption. The outcomes underscore the potential of CNTFETs as promising alternatives in the progression of digital design, offering heightened efficiency and diminished power consumption.

Two-dimensional van der Waals ferroelectric field-effect transistors toward nonvolatile memory and neuromorphic computing

With the gradual decline in Moore's law, traditional silicon-based technologies have encountered numerous challenges and limitations, prompting researchers to seek solutions. Two-dimensional (2D) van der Waals (vdWs) ferroelectric (Fe) field-effect transistors (FETs) (2D vdWs FeFETs) are devices that integrate emerging 2D vdWs ferroelectric materials into the transistor structures. In comparison with traditional complementary metal oxide semiconductor FETs (COMSFETs), they exhibit superior performance, including lower power consumption, higher switching speed, and improved stability. The vdWs FeFETs are anticipated to surpass the limits imposed by Moore's law, offering increased possibilities and opportunities for research and application in the field of nanoelectronics, particularly in nonvolatile memory (NVM) and neuromorphic computing (NMC). In this review, we summarize the recent research progress of vdWs FeFETs and elucidate their development origin, basic structure, and working mechanism. Furthermore, we explore the application of vdWs FeFETs in NVM, NMC, and large-scale arrays. Finally, we highlight the prominent challenges and future directions in this field.

An Efficient Design of a Parallel Prefix Adder based on QCA Technology

This paper presents an optimized Parallel Prefix Adders (PPA) based on Quantum dot Cellular Automata (QCA) technology. PPA presents the most used block in Arithmetic Logic Units (ALU) which presents a fundamental part in several digital integrated circuits. The classical implementation method of PPA based on traditional Complementary Metal Oxide Semiconductor (CMOS) Technology presents several problems in terms of frequency, power consumption, surface and others. The QCA technology offers several features such as ultralow power consumption, small size, and can operate up to 1 THz. In this work, a 4-bit Parallel Prefix Adder with a new prefix low area and high speed is proposed. The proposed design is based on a half-adder circuit and other logic gates. These designs were tested and simulated using the freely known QCA Designer Tool version 2.0.3. and QCA pro. The proposed Half-adder presents a reduction of 23% 46% and 36% in terms of cell count, latency and power consumption, respectively compared to existing designs. The proposed PPA design shows almost an optimization of 5% in area and 58% in latency compared to the RCA design. The proposed circuit present an optimization of 20% in term of energy consumption compared to the existing PPA 4-bit Brent Kung Adder design.

A sensory memory processing system with multi-wavelength synaptic-polychromatic light emission for multi-modal information recognition

Realizing multi-modal information recognition tasks which can process external information efficiently and comprehensively is an urgent requirement in the field of artificial intelligence. However, it remains a challenge to achieve simple structure and high-performance multi-modal recognition demonstrations owing to the complex execution module and separation of memory processing based on the traditional complementary metal oxide semiconductor (CMOS) architecture. Here, we propose an efficient sensory memory processing system (SMPS), which can process sensory information and generate synapse-like and multi-wavelength light-emitting output, realizing diversified utilization of light in information processing and multi-modal information recognition. The SMPS exhibits strong robustness in information encoding/transmission and the capability of visible information display through the multi-level color responses, which can implement the multi-level pain warning process of organisms intuitively. Furthermore, different from the conventional multi-modal information processing system that requires independent and complex circuit modules, the proposed SMPS with unique optical multi-information parallel output can realize efficient multi-modal information recognition of dynamic step frequency and spatial positioning simultaneously with the accuracy of 99.5% and 98.2%, respectively. Therefore, the SMPS proposed in this work with simple component, flexible operation, strong robustness, and highly efficiency is promising for future sensory-neuromorphic photonic systems and interactive artificial intelligence.

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Decreasing power consumption is the leading challenge for very-large-scale-integrated (VLSI) designers. This paper introduces an innovative prototype for a power-efficient standard or a fully-adiabatic binary-coded-decimal (BCD) 8421 to Excess-3 (XS-3) code converter. The proposed design is compared with traditional complementary metal oxide semiconductor (CMOS) as well as two popular fully adiabatic logic families: adiabatic dynamic CMOS logic (ADCL) and two phase clocked adiabatic static CMOS logic (2PASCL). This investigation was conducted at frequencies ranging from 100 to 900 MHz. The circuit employs 0.3 μm CMOS technology, with channel length and width set at 0.3 μm and 0.75 μm, respectively. The power savings for the proposed logic at 500 MHz when compared to standard CMOS logic, ADCL, and 2PASCL are 54.54%, 28.57%, and 16.67%, respectively.

Organic Memristor with Synaptic Plasticity for Neuromorphic Computing Applications

Memristors have been considered to be more efficient than traditional Complementary Metal Oxide Semiconductor (CMOS) devices in implementing artificial synapses, which are fundamental yet very critical components of neurons as well as neural networks. Compared with inorganic counterparts, organic memristors have many advantages, including low-cost, easy manufacture, high mechanical flexibility, and biocompatibility, making them applicable in more scenarios. Here, we present an organic memristor based on an ethyl viologen diperchlorate [EV(ClO4)]2/triphenylamine-containing polymer (BTPA-F) redox system. The device with bilayer structure organic materials as the resistive switching layer (RSL) exhibits memristive behaviors and excellent long-term synaptic plasticity. Additionally, the device's conductance states can be precisely modulated by consecutively applying voltage pulses between the top and bottom electrodes. A three-layer perception neural network with in situ computing enabled was then constructed utilizing the proposed memristor and trained on the basis of the device's synaptic plasticity characteristics and conductance modulation rules. Recognition accuracies of 97.3% and 90% were achieved, respectively, for the raw and 20% noisy handwritten digits images from the Modified National Institute of Standards and Technology (MNIST) dataset, demonstrating the feasibility and applicability of implementing neuromorphic computing applications utilizing the proposed organic memristor.

Design optimization of a silicon-germanium heterojunction negative capacitance gate-all-around tunneling field effect transistor based on a simulation study

The steep sub-threshold swing of a tunneling field-effect transistor (TFET) makes it one of the best candidates for low-power nanometer devices. However, the low driving capability of TFETs prevents their application in integrated circuits. In this study, an innovative gate-all-around (GAA) TFET, which represents a negative capacitance GAA gate-to-source overlap TFET (NCGAA-SOL-TFET), is proposed to increase the driving current. The proposed NCGAA-SOL-TFET is developed based on technology computer-aided design (TCAD) simulations. The proposed structure can solve the problem of the insufficient driving capability of conventional TFETs and is suitable for sub-3-nm nodes. In addition, due to the negative capacitance effect, the surface potential of the channel can be amplified, thus enhancing the driving current. The gate-to-source overlap (SOL) technique is used for the first time in an NCGAA-TFET to increase the band-to-band tunneling rate and tunneling area at the silicon–germanium heterojunction. By optimizing the design of the proposed structure via adjusting the SOL length and the ferroelectric layer thickness, a sufficiently large on-state current of 17.20 μA can be achieved and the threshold voltage can be reduced to 0.31 V with a sub-threshold swing of 44.98 mV/decade. Finally, the proposed NCGAA-SOL-TFET can overcome the Boltzmann limit-related problem, achieving a driving current that is comparable to that of the traditional complementary metal–oxide semiconductor devices.

Energy-Efficient circuits with improved diode free adiabatic logic design methodology

This paper demonstrates a detailed analysis of an unique improved diode-free adiabatic logic (IDFAL) circuit. The IDFAL is operated based on adiabatic switching principle. To indicate the circuit effectiveness, numerous analyses are carried out on different complementary metal oxide semiconductor (CMOS) technology nodes. Logic circuits, viz., NOT and NAND are analyzed and simulated using the traditional CMOS design style and some popular adiabatic logic design techniques: two-phase clocked adiabatic static CMOS logic (2PASCL), diode free adiabatic logic (DFAL), adiabatic dynamic CMOS logic (ADCL), two-phase adiabatic dynamic CMOS logic (2PADCL), quasi-static energy recovery logic (QSERL), and clocked CMOS adiabatic logic (CCAL). The results are compared with the proposed design (IDFAL) at various operating frequencies. The results revealed that the IDFAL inverter circuit has the least power delay product (PDP) among the reported adiabatic design methodologies and saves 91.59 % over the counter-part CMOS inverter at 16 nm high-performance predictive technologies (HP_PTM).

The Trend of 2D Transistors toward Integrated Circuits: Scaling Down and New Mechanisms.

2D transition metal chalcogenide (TMDC) materials, such as MoS2 , have recently attracted considerable research interest in the context of their use in ultrascaled devices owing to their excellent electronic properties. Microprocessors and neural network circuits based on MoS2 have been developed at a large scale but still do not have an advantage over silicon in terms of their integrated density. In this study, the current structures, contact engineering, and doping methods for 2D TMDC materials for the scaling-down process and performance optimization are reviewed. Devices are introduced according to a new mechanism to provide the comprehensive prospects for the use of MoS2 beyond the traditional complementary-metal-oxide semiconductor in order to summarize obstacles to the goal of developing high-density and low-power integrated circuits (ICs). Finally, prospects for the use of MoS2 in large-scale ICs from the perspectives of the material, system performance, and application to nonlogic functionalities such as sensor circuits and analogous circuits, are briefly analyzed. The latter issue is along the direction of "more than Moore" research.

Layout Design of Row Decoder using Cadence

Abstract: Logic circuits, data transport circuits, and analogue to digital conversions all frequently employ decoders. For the line decoders, a mixed logic design approach incorporating transmission gate logic, pass transistor logic, and complementary metaloxide semiconductor (CMOS) technology is employed to achieve the desired performance and operation. A unique topology is proposed for the 2 to 4 decoders, which calls for a topology with fourteen transistors to reduce operating power and transistor count and a topology with fifteen transistors to achieve high power and low delay performance. For a total of four new designs, standard and inverting decoders are created for each situation. All of the suggested decoders have a low transistor count in comparison to their traditional CMOS architectures. Last but not least, a number of suggested solutions demonstrate a notable improvement in operating power and propagation latency, exceeding CMOS in virtually all instances

Возможности датчиков изображения с фотонным лавинным диодом

In many fields of science and technology there is a need to record fast running processes and phenomena, often occurring in low light conditions. In such cases, there is a need to use highly sensitive image sensors. Such sensors can be constructed on the basis of photon avalanche diodes capable of capturing even single photons. However, creating this type of sensor with high performance, in particular, with high resolution, presents a number of technological challenges, as they are more complex than traditional CMOS (Complementary Metal–Oxide–Semiconductor) and CCD (Charge-Coupled Device) sensors. Using recent advances and new circuitry, Canon created the first megapixel image sensor with a photon avalanche diode (Single Photon Avalanche Diode, SPAD). In this article, in addition to general issues related to image sensors with photon avalanche diode, the design, operation, characteristics, features and possible applications of Canon’s SPAD megapixel sensor are discussed. In particular, the methods of photon counting and time-of-flight are discussed, as well as the dynamic range of the sensor, the possibilities of sensor application for imaging in the infrared range, and the prospects for wide application of SPAD sensors in the near future. As a result, it can be noted that in addition to direct use for obtaining high-quality 2D-images of fast processes running in low light conditions, such a sensor can be used for taking images in the infrared range, to obtain 3D-images for xReality, measuring the distance to objects, obtaining a depth map, as well as in areas of science and technology that are new for such devices, including, for example, quantum computing.

Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques

Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

Quantum-dot cellular automata as a potential technology for designing nano-scale computers: Exploring the state-of-the-art techniques and suggesting the opportunities for the future

Leakage-power usage, physical-scalability constraints, and short-channel impacts are major issues with traditional Complementary Metal-Oxide-Semiconductor (CMOS) technology. Furthermore, as device dimensions reduce, traditional transistor-based CMOS technology faces significant challenges because of physical limitations like ultra-thin gate oxides, leakage currents, and high power consumption at nano-scale regimes. Numerous experiments on nano-scale architectures have resulted from these flaws. As a challenger to conventional CMOS-based technology, Quantum Dot Cellular Automata (QCA) presents a fundamentally novel computational foundation for designing digital logic circuits employing quantum dots contained in the potential well to process and transmit information at the nano level efficiently. Despite the importance of reviewing and studying QCA as a viable technology for creating nano-scale computers, there is no comprehensive and organized literature evaluation of the status of the mechanics in this sector. As a consequence, we examine current quantum computing techniques in five areas and make recommendations for future research. The findings reveal that quantum computers are infamously prone to faults and have high latency. Unfortunately, quantum error correction systems are still unavailable for current and near-future quantum computers. This research shows that quantum computation will require significant algorithmic advancements before solving quantum challenges.

Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits

The quest for efficient technologies beyond the traditional CMOS (Complementary-Metal-Oxide-Semiconductor) technology has led researchers to explore newer technologies like the CNFET(Carbon-Nanotube-Field-Effect-Transistor). CNFETs are being used to design and implement various ternary logic circuits. Multivalued logic (MVL) requires multiple threshold voltages that are possible to obtain using CNFETs by modifying the physical dimensions of their CNTs (Carbon Nano Tubes). The ternary sequential logic circuits like ternary D-latch, D-flipflop, and counters existing in literature have been implemented either using STIs (Standard Ternary Inverters) or successor-predecessor circuits. This paper proposes a new design methodology for a ternary D-flipflop that uses a ternary buffer and two STIs designed using two power supplies. Two hybrid architectures for ternary D-flipflop designs have also been proposed that are implemented using a combination of ternary buffer, STIs and successor-predecessor circuits. Using these ternary D-flipflop designs, ternary 3- trit synchronous and asynchronous counters are designed in this paper. The proposed designs are simulated using HSPICE and a standard Stanford CNFET model. The proposed ternary D-flipflops show an improvement of up to 93.5% in power, up to 44.7% in delay and up to 94.3% in PDP compared to existing designs.

Transistor Count Reduction Technique for Clockfree Null-convention Arithmetic Logic Circuits

Null Convention Logic (NCL) is a robust clock-less technique for designing asynchronous delay-insensitive circuits. The traditional complementary metal oxide semiconductor (CMOS) approach is often used for designing NCL circuits, which tends to occupy a large area. To address this issue, a low power design technique Gate Diffusion Input (GDI) is introduced for designing the NCL circuits. This GDI design methodology is the promising alternative for the static CMOS designs, which allows the reduction in area and power consumption while maintaining the low complexity of the logic design. In this paper, a novel GDI based NCL designs are proposed and designed. However, the voltage swings in the GDI approach leads to the considerable amount of voltage drop at the output. This limitation is addressed by using low threshold transistors where a voltage drop is expected, and high threshold transistors are used for the regenerative inverters at the output. The proposed approach has been verified by designing the NCL Ripple Carry Adder (RCA), Unpipelined multiplier, pipelined multiplier and Unpipelined ALU by using the GDI technique. These models are designed and simulated using Cadence Virtuoso and an average of 13.5 % reduction in the transistor count is observed for these GDI based NCL models when compared to the CMOS models.

Module‐based design method using clocking scheme for quantum‐dot cellular automata

AbstractQuantum‐dot cellular automata (QCA) is a field‐coupled nanotechnology with unique computing paradigms to be one of the strong alternatives to replace the traditional complementary metal oxide semiconductor (CMOS) in the future in theory. With the development of its fabrication technique and increasing circuit scale, the modular design method of QCA circuits is promoted, which consists at least of two connotations: designing appropriate modules for circuits and allocating applicable clock to circuits. In this paper, a module‐based design method using a clocking scheme (MCS) in QCA is proposed, which can be categorized into the modular design methodology. A complete module library for constructing circuits and a flexible clocking scheme for driving them are correspondingly proposed for the MCS method. Compared to previous design methods, its library includes not only active modules but also passive modules to connect active modules to construct circuits, so that more complex circuits can then be synthesized with them. After that, the efficient clocking scheme with fixed clock zones and signal propagation directions that is designed according to the characteristics of the proposed library solves the clock allocation problem in complex circuits. Full adder, multi‐bit adder, D flip‐flop, and multi‐bit D flip‐flop are taken as examples to illustrate the performances of the proposed MCS method in designing combinational and sequential circuits, respectively. The experimental results show that this method is more suitable for modular design in QCA in contrast to previous methods.