Power Tradeoffs Research Articles

Tunable Class AB CMOS Gm-C Filter Based on Quasi-Floating Gate Techniques

A tunable CMOS Gm-C channel-select low-pass filter is presented. Class AB operation overcomes the dynamic range versus static power tradeoff of conventional channel-select filter topologies. Programmable transconductors are designed using quasi-floating gate transistors, which provide class AB operation without requiring extra supply voltage or power requirements and keeping accurately set quiescent currents. The filter can be applied to channel selection in highly integrated, low power zero-IF wireless receivers. For example, its frequency tuning range and linearity makes it suitable for a dual-mode Bluetooth/ZigBee zero-IF receiver. Measurement results for a test chip prototype in a 0.5 μm standard CMOS process are presented, showing a THD <; -55 dB for an input of 1.2 Vpp, which corresponds to peak currents 300% larger than the bias current.

A multiple comparison procedure for hypotheses with gatekeeping structure

We develop gatekeeping procedures that focus on comparing multiple treatments with a control when there are multiple endpoints. Our procedures utilize estimated correlations among individual test statistics without parametric assumptions. We make comparisons with other gatekeeping procedures with respect to properties of the trade-off in statistical power between families of hypotheses. We introduce a reward function to facilitate these comparisons. We illustrate our methods by simulation and an analysis of data from a randomized, multi-armed clinical trial. Copyright 2013, Oxford University Press.

What Links Gait Speed and MCI With Dementia? A Fresh Look at the Association Between Motor and Cognitive Function

What Links Gait Speed and MCI With Dementia? A Fresh Look at the Association Between Motor and Cognitive Function

Software Defined Radio Equipment: What's the Best Design Approach to Reduce Power Consumption and Increase Reconfigurability ?

3 ENIS/CES, Route Soukra B.P. 1173, 3038 Sfax, Tunisie ABSTRACTarticle explores several hardware design methods used to implement a reconfigurable software defined radio system. The promise of software defined radios for rapidly changing the operating characteristics of radios suggests further an exciting new method to create opportunities and means for interoperability among and between any number of different radio systems. The possibilities of run-time reconfiguration techniques are explained and quantified. In this article, we are going to limit our discussion to examine the reconfigurability and low power trade-offs between: (i) building dedicated functional modules providing high performance at a high cost (Velcro approach), versus (ii) parameterizable function blocks used in FPGA-based system development, versus (iii) dynamic partial reconfiguration which is the ability to reconfigured a portion of the FPGA while the remainder is still in operation. The main objective here is to explore and discuss the best method to design a reconfigurable, a high performance and a low power consumption software defined equipment.

Sigma-Delta Modulation Based Digital Filter Design Techniques in FPGA

In this paper efficient digital filter design techniques categorized as sigma-delta modulation based short word length (SWL) and multibit (or contemporary) techniques are reviewed in terms of hardware complexity, area, performance and power tradeoffs, synthesis issues, and algorithm versatility. More recent, general purpose DSP applications including classical LMS algorithms reported using sigma-delta modulation encoding are reviewed thoroughly. A small number of basic arithmetic circuits designed using sigma-delta modulation encoding and synthesized by using FPGAs are also described. Finally, recent FPGA based area-performance-power analysis of single-bit ternary FIR filtering is discussed and compared to its corresponding multi-bit system. This work shows that in most cases single-bit ternary FIR-like filters are able to outperform their equivalent multi-bit filters in terms of area, power, and performance.

Using Datacenter Simulation to Evaluate Green Energy Integration

Many simulators are available to evaluate performance and power tradeoffs in datacenters. The authors use one such simulator to demonstrate that by accurately provisioning green energy availability for longer time intervals, green energy prediction can improve overall energy efficiency.

Interface circuit synthesis of system-on-chip

Most of the intellectual properties (IPs) of system-on-chip (SoC) are provided by different vendors, and thus they may have various characteristics, making the interface circuit synthesis of SoC a time-consuming and error-prone process. The main contribution of this article is to present an interface synthesis algorithm for power minimisation in interface circuit design of SoC. Moreover, we also study the power and area trade-off in interface circuit synthesis of such systems. By starting from the power-minimal solution, we perform a sequence of power relaxation operations and area-minimising procedures to produce a set of solutions for a given SoC interface circuit design with power and area trade-off considerations. The experimental results demonstrate the effectiveness of our algorithms.

New Space Shift Keying Modulation with Hamming Code-Aided Constellation Design

A modulation scheme that maps the information onto the antenna indices, such as space shift keying (SSK) and its generalized form (namely, generalized SSK or GSSK), presents an attractive option for the emerging large-scale MIMO system due to the reduced algorithm and hardware cost. In this letter, we present a new modulation scheme in this category, where we propose use of the Hamming code construction technique to systematically design the constellation. An illustrative example and experimental studies demonstrate that the proposed scheme introduces rich design flexibility and achieves better transmission rate, performance, and power tradeoffs with comparable hardware costs as compared with existing schemes.

Power-delay Trade-offs in CMOS Circuits Using Self-bias Transistors

Power dissipation and propagation delay are contradicting factors in the design of VLSI CMOS circuits. This paper investigates CMOS circuits with Self-Bias Transistors (SBTs) connected between the pull-up/down network and the supply rails. Previous research on circuits with SBTs shows substantial reduction in leakage power of combinational circuits. We extend the analyses by studying both static and dynamic power and also propagation delay for combinational as well as sequential circuits. Transistor-level dual-Vt technique is employed for combinational circuits with SBTs to achieve a good power and delay trade-off by selecting different transistors in the circuit to have different Vt. Extensive HSPICE simulations were performed with 0.18 μm CMOS technology. Results show that on average, a 45% reduction in static power and 17% reduction in dynamic power can be achieved by employing SBTs in combinational CMOS circuits. Similar results for sequential CMOS circuits are also included. Simulation results for propagation delay and power-delay trade-off are also presented.

Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)

As process technology scales, the design effort and nonrecurring engineering (NRE) costs associated with the development of integrated circuits is becoming extremely high. Structured ASICs offer one solution to these problems. However, to realize their full potential, their performance and cost advantages, architectures, and CAD must be fully understood. We believe that this can lead to wider adoption of structured ASICs. In this paper, we take a step in this direction and investigate the area, delay, power, and cost tradeoffs in metal-programmable structured ASICs (MPSAs). In particular, we quantify the impact of the number of user-defined (custom) metal mask layers on these metrics. Results indicate that for lowest cost, the number of custom layers should be minimized, especially for small die sizes (e.g., less than 100 mm2). Delay and power, however, can be improved by a few additional custom layers. With two custom metal layers, MPSAs can be 2x - 10x cheaper than cell-based ICs (CBICs).

AND-OR-XOR NETWORK SYNTHESIS WITH AREA-POWER TRADE-OFF

In this paper, a heuristic based on genetic algorithm to realize multi-output Boolean function as three-level AND-OR-XOR network performing area power trade-off is presented. All the previous works dealt with the minimization of number of product terms only in the two sum-of-product-expressions representing a Boolean function during AND-OR-XOR network synthesis. To the best of knowledge this is the first ever effort to incorporate total power, that is, dynamic and leakage power along with the area (in terms of number of product terms) during three-level AND-OR-XOR networks synthesis. The synthesis process, without changing the delay performance results in lesser number of product terms compared to those reported in the literature. It also enumerates the trade-offs present in the solution space for different weights associated with area, dynamic power, and leakage power of the resulting circuit.

Architecture of source-drain cavity of a p-channel field effect transistor for embedding with epitaxial SiGe for enhanced performance

Increase in power consumption in field effect transistors has been curtailed in recent years by introduction of mechanical stress to achieve device speed gain over and above the traditional speed vs. power tradeoffs achieved only by scaling gate lengths. Increasingly, the source-drain region of p-channel field effect transistors are etched and epitaxial SiGe re-grown in the cavity to enhance hole mobility. However, the addition of stress as a method to improve performance would add to the process variability beyond the traditional source of lithography, now related to structure and dimension of the cavity and composition of SiGe. In this paper, compressive stress induced in the channel was directly measured using synchrotron x-ray diffraction. The samples were a set of gratings designed to map the transistor performance with varying design space. The x-ray beam was systematically stepped across the gratings at an interval of 200 nm and diffraction data collected to assess the extent of stress field. Diffraction space maps were created around the symmetric (004) and asymmetric (115) planes. Strain was deduced from Si peak shift and stress calculated from the Si elastic constants. Diffraction space maps around the asymmetric plane were used to deduce the mechanism and subsequent relaxation of strain. Diffraction data collected with x-ray beam placement close to the Si-SiGe vertical interface provided information from lateral SiGe epitaxy on the (110) plane. The presence of strained SiGe peak exhibiting tilt as well as “relaxed” SiGe peak surrounded by diffuse scattering due to dislocations were observed. The use of non-selective etch process resulted in cavity formation with multiple crystallographic planes. The subsequent relaxation mechanism that was dependent on the formation of misfit dislocations was perturbed, possibly due to pinning of the dislocations at the intersection of two crystallographic planes and served as the source of variability. Measured stress variation from 90 to 220 MPa was seen that resulted in estimated drive current enhancement variability from 5% to 15%. The maximum strain was seen where the SiGe film saw no relaxation and the energy formed due to hetero-epitaxy was transferred elastically as channel stress. The elastic relaxation was also accompanied by formation of tilted boundary. Based on these findings, the design of an ideal cavity that would maximize strain and minimize variability with layout was proposed.

Fundamental trade-offs on green wireless networks

Traditional design of mobile wireless networks mainly focuses on ubiquitous access and large capacity. However, as energy saving and environmental protection become a global demand and inevitable trend, wireless researchers and engineers need to shift their focus to energy-efficiency oriented design, that is, green radio. In this paper, we propose a framework for green radio research and integrate the fundamental issues that are currently scattered. The skeleton of the framework consists of four fundamental tradeoffs: deployment efficiency - energy efficiency tradeoff, spectrum efficiency - energy efficiency tradeoff, bandwidth - power tradeoff, and delay - power tradeoff. With the help of the four fundamental tradeoffs, we demonstrate that key network performance/cost indicators are all stringed together.

A Micropower Low-Noise Neural Recording Front-End Circuit for Epileptic Seizure Detection

This paper describes a micropower low-noise neural front-end circuit capable of recording epileptic fast ripples (FR). The front-end circuit consisting of a preamplifier followed by a 6th-order bandpass filter is designed for signal sensing in a future epileptic deep brain stimulator. A current-splitting technique is combined with an output-branch current scaling technique in a folded-cascode amplifier structure to improve the noise and power tradeoff in the preamplifier. In measurements, the preamplifier exhibits 39.4 dB DC gain, 0.36 Hz to 1.3 kHz of -3 dB bandwidth, and 3.07 μVrms total input-referred noise while consuming 2.4 μW from a 2.8 V power supply provided by an on-chip regulator circuit. A noise efficiency factor (NEF) of 3.09 is achieved with minimal power consumption and is one of the lowest published to date. The 6th-order follow-the-leader feedback elliptic bandpass filter passes FR signals and provides -110 dB/decade attenuation to out-of-band frequency components. In measurements, the entire front-end circuit achieves a mid-band gain of 38.5 dB, a bandwidth from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. To the authors' knowledge, the proposed epileptic seizure- detection system is the first to achieve the FR-recording functionality. The chip is fabricated in a standard 0.6 μm CMOS process. Die size is 0.45 mm2.

Optimisation of the Cost / Power Trade-offs Associated with Solvent Absorption Carbon-capture Plants

The addition of carbon capture and storage to a power station will impact the net power generated and increase the cost of electricity produced from the power stations. A method is presented to help design the carbon capture and compression process retrofitted to the power station. It combines simulation, automated heat integration and multi-objective optimisation. The methodology is applied to a coal fired power station combined with potassium carbonate based solvent absorption. The energy penalty, the ratio of the change in efficiency of the power station due to the addition of CCS over the efficiency of the original power station, to capture 90 % of the CO2 emissions can be reduced from 38 to 14 % using this method. However to minimise the cost of electricity, more modest reductions in energy penalty of 22 – 25 % are recommended.

GPU Accelerated H.264 Video Compression for Broadcast

In recent years, the ability to perform massive parallel computations has become readily available on every desktop due to improved graphic processors and new programming tools such as CUDA. The standard central processing units (CPUs) are also evolving rapidly in the same direction, making this technology even more accessible. Video compression is an illustrative example of an area where the speed/computation power trade-off is especially steep. To render all the features of the modern H.264 compression standard, a supercomputing level of power might be necessary. The modern graphics processing unit (GPU) and the next generation of the CPU could deliver the required computation power. We investigate what can be done to exploit the features of the modern GPUs for H.264 compression and how the new video compression standards such as H.265 might be adopted in the future of massive parallel processing.

Pulse compression of a high-power thin disk laser using rod-type fiber amplifiers

We report on two pulse compressors for a high-power thin disk laser oscillator using rod-type fiber amplifiers. Both systems are seeded by a standard SESAM modelocked thin disk laser that delivers 16 W of average power at a repetition rate of 10.6 MHz with a pulse energy of 1.5 μJ and a pulse duration of 1 ps. We discuss two results with different fiber parameters with different trade-offs in pulse duration, average power, damage and complexity. The first amplifier setup consists of a Yb-doped fiber amplifier with a 2200 μm2 core area and a length of 55 cm, resulting in a compressed average power of 55 W with 98-fs pulses at a repetition rate of 10.6 MHz. The second system uses a shorter 36-cm fiber with a larger core area of 4500 μm2. In a stretcher-free configuration we obtained 34 W of compressed average power and 65-fs pulses. In both cases peak powers of > 30 MW were demonstrated at several μJ pulse energies. The power scaling limitations due to damage and self-focusing are discussed.

Algorithmic Optimization of BDDs and Performance Evaluation for Multi-level Logic Circuits with Area and Power Trade-offs

Binary Decision Diagrams (BDDs) can be graphically manipulated to reduce the number of nodes and hence the area. In this context, ordering of BDDs play a major role. Most of the algorithms for input variable ordering of OBDD focus primarily on area minimization. However, suitable input variable ordering helps in minimizing the power consumption also. In this particular work, we have proposed two algorithms namely, a genetic algorithm based technique and a branch and bound algorithm to find an optimal input variable order. Of course, the node reordering is taken care of by the standard BDD package buddy-2.4. Moreover, we have evaluated the performances of the proposed algorithms by running an exhaustive search program. Experi-mental results show a substantial saving in area and power. We have also compared our techniques with other state-of-art techniques of variable ordering for OBDDs and found to give superior results.

Speed and Leakage Power Trade-off in Various SRAM Circuits

The growing demand of multimedia rich applications in handled portable devices continuously driving the need for large and high speed embedded Static Random Access Memory (SRAM) to enhance the system performance. Many circuit techniques, e.g. body bias, bit charge recycling etc., have been proposed to expand design margins at low voltage operation while reducing leakage current at standby mode, but the performance is analyzed at the cost of speed and this issue is not addressed widely. Also due to continuous scaling of CMOS, the process variations also affect the performance of SRAMs. This paper presents the analysis of low leakage SRAM along with the speed factor.

Systematic design of wideband ΔΣ modulators for WiFi/WiMAX receivers

Modern multi-standard receivers in deep-submicron technologies pose significant design challenges on the analog baseband. Moving this analog filtering to the digital domain simplifies the design, yielding a process-scalable implementation. However, analog-to-digital converter (ADC) specifications now become more stringent and must be obtained by comprehending the standard and the system. Assuming a receiver NF of 5.96 dB and SNR degradation of 0.36 dB by the ADC, the proposed dual-mode WiFi/WiMAX receiver attains an input sensitivity of ?74 dBm (20 MHz channel bandwidth). To accommodate the high dynamic range and the anti-alias rejection needed for the system, a Delta-Sigma (ΔΣ) ADC is proposed. Single-loop and Multi-Stage Noise-Shaping (MASH) architectures that achieve a SNR of 69 dB at a low oversampling ratio (OSR) of 8 for a conversion bandwidth of 40 MHz (108 Mbps, OFDM) are investigated at system level. Based on thermal noise, harmonic distortion, and power tradeoffs, a ΔΣ ADC design that meets the design specifications is presented.