The proposed upgrade of the LHC, the Super-LHC, will tenfold the peak luminosity to 1035 cm−2s−1 at a center of mass energy of (s)1/2 = 14 TeV. Depending on the upgrade scheme up to 400 events per bunch crossing have to be considered, a challenge especially for the tracking detectors and trigger systems of CMS and ATLAS. The ATLAS upgrade program foresees a new all-silicon inner detector and modifications to the trigger system. Exploiting track information already on the first trigger level, being only marginally done in the current ATLAS detector, is a promising option to reduce the L1 trigger rate and bandwidth. We describe a possible realisation of a Level 1 Track Trigger based on Content-Addressable-Memories and the impact of the new inner detector design on the track trigger performance.