Trace Buffer Research Articles

Assertion-Based Validation using Clustering and Dynamic Refinement of Hardware Checkers

Post-silicon validation is a vital step in System-on-Chip (SoC) design cycle. A major challenge in post-silicon validation is the limited observability of internal signal states using trace buffers. Hardware assertions are promising to improve observability during post-silicon debug. Unfortunately, we cannot synthesize thousands (or millions) of pre-silicon assertions as hardware checkers (coverage monitors) due to hardware overhead constraints. Therefore, we need to select the most profitable assertions based on design constraints. However, the design constraints can also change dynamically during the device lifetime due to changes in use-case scenarios as well as input variations. Therefore, assertion selection needs to dynamically adapt based on changing circumstances. In this article, we propose an assertion-based post-silicon validation framework to address the above challenges. Specifically, this article makes two important contributions. We propose a clustering-based assertion selection technique that can select the most profitable pre-silicon assertions to maximize the fault coverage. We also present a cost-aware dynamic refinement technique that can select beneficial hardware checkers during runtime based on changing design constraints. Experimental evaluation demonstrates that our proposed pre-silicon assertion selection can outperform state-of-the-art assertion ranking methods (Goldmine and HARM). The results also highlight that our proposed post-silicon dynamic refinement can accurately predict area (less than 5% error) and power consumption (less than 3% error) of hardware checkers at runtime. This accurate prediction enables the identification of the most profitable hardware checkers based on design constraints.

Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers

Large volumes of on-chip and off-chip memory are required by contemporary applications. Emerging non-volatile memory technologies including STT-RAM, PCM, and ReRAM are becoming popular for on-chip and off-chip memories as a result of their desirable properties. Compared to traditional memory technologies such as SRAM and DRAM, they have minimal leakage current and high packing density. Non Volatile Memories (NVM), however, have a low write endurance, a high write latency, and high write energy. Non-volatile Single Level Cell (SLC) memories can store a single bit of data in each memory cell, whereas Multi Level Cells (MLC) can store two or more bits in each memory cell. Although MLC NVMs have substantially higher packing density than SLCs, their lifetime and access speed are key concerns. For a given cache size, MLC caches consume 1.84× less space and 2.62× less leakage power than SLC caches. We propose Trace buffer Assisted Non-volatile Memory Cache (TANC), an approach that increases the lifespan and performance of MLC-based last-level caches using the underutilized Embedded Trace Buffers (ETB). TANC improves the lifetime of MLC LLCs up to 4.36× and decreases average memory access time by 4% compared to SLC NVM LLCs and by 6.41× and 11%, respectively, compared to baseline MLC LLCs.

Hardware-Assisted Malware Detection and Localization using Explainable Machine Learning

Malicious software, popularly known as malware, is widely acknowledged as a serious threat to modern computing systems. Software-based solutions, such as anti-virus software (AVS), are not effective since they rely on matching patterns that can be easily fooled by carefully crafted malware with obfuscation or other deviation capabilities. While recent malware detection methods provide promising results through effective utilization of hardware features, the detection results cannot be interpreted in a meaningful way. In this paper, we propose a hardware-assisted malware detection framework using explainable machine learning. This paper makes three important contributions. First, we theoretically establish that our proposed method can provide interpretable explanations for classification results to address the challenge of transparency. Next, we show that the explainable outcome through effective utilization of hardware performance counters and embedded trace buffer can lead to accurate localization of malicious behavior. Finally, we have performed efficiency versus accuracy trade-off analysis using decision tree and recurrent neural networks. Extensive evaluation using a wide variety of real-world malware datasets demonstrates that our framework can produce accurate and human-understandable malware detection results with provable guarantees.

Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty

Due to limited on-chip caching, data-driven applications with large memory footprint encounter frequent cache misses. Such applications suffer from recurring miss penalty when they re-reference recently evicted cache blocks. To meet the worst-case performance requirements, Network-on-Chip (NoC) routers are provisioned with input port buffers. However, recent studies reveal that these buffers remain underutilised except during network congestion. Trace buffers are Design-for-Debug (DfD) hardware employed in NoC routers for post-silicon debug and validation. Nevertheless, they become non-functional once a design goes into production and remain in the routers left unused. In this article, we exploit the underutilised NoC router buffers and the unused trace buffers to store recently evicted cache blocks. While these blocks are stored in the buffers, future re-reference to these blocks can be replied from the NoC router. Such an opportunistic caching of evicted blocks in NoC routers significantly reduce the miss penalty. Experimental analysis shows that the proposed architectures can achieve up to 21 percent (16 percent on average) reduction in miss penalty and 19 percent (14 percent on average) improvement in overall system performance. While we have a negligible area and leakage power overhead of 2.58 and 3.94 percent, respectively, dynamic power reduces by 6.12 percent due to the improvement in performance.

Runtime Malware Detection Using Embedded Trace Buffers

Anti-virus software (AVS) tools are used to detect malware in a system. However, AVS are vulnerable to attacks. A malicious entity can exploit these vulnerabilities to subvert the AVS. Recently, hardware components such as hardware performance counters have been used for malware detection. In this article, we propose preempts malware by examining embedded processor traces (PREEMPT), a zero overhead, high-accuracy, low-latency technique to detect malware by repurposing embedded trace buffer (ETB), a debug hardware component available in most modern processors. The ETB is used for postsilicon validation and debug and allows us to control and monitor the internal activities of a chip, beyond what is provided by the input/output pins. PREEMPT combines these hardware-level observations with machine learning-based classifiers to preempt malware before it causes damage. The benefits of reusing ETB for malware detection include the increased robustness against attacks and no performance penalties. PREEMPT can detect malware on an OpenSPARC T1 core running Linux operating system with a F1-score of 96.6%.

Improved design debugging architecture using low power serial communication protocols for signal processing applications

Now-a-days FPGA designers are facing the problem of unprecedented challenges in debugging their designs. In the past, designers debugged their FPGAs by plugging them onto a board and then analyzing them with probes and logic analyzers. But right now the vendors of FPGA are offering tools that make it somewhat easier to probe internal design signals inside the FPGA, Once unexpected behavior is observed, on-chip debug is notoriously difficult; typically a design is instrumented with on-chip trace buffers that record the run-time behavior for later interrogation. Based on the demand for verification leads to an increase in FPGA-based tools that improves the performance of the architecture. The low power communication protocols can run at much higher operating frequencies with less area.FPGAs provide a promising implementation option for many DSP applications particularly in speech signal processing devices such as data converters, digital filters, etc. This work improves the performance of current debugging techniques and makes them more reliable. This work proposes a novel design debugging architecture based on implementation of reconfigurable insertion technique with the help of low power communication protocols used in the FIR filter to debug the entire architecture with less area. If there is any possibility of bug occurs in the UART protocol then the data is transferred through SPI protocol. SPI protocol worked in the operating frequency of 330.12 MHz. According to the power consumption, the UART protocol consumes 0.0135W which is far better than other protocols like SPI, I2C etc. Moreover, the area overhead is reduced. This is achieved by implementing the extra instrumentation. The design debugging architecture is developed using Verilog HDL and implemented on FPGA with the help of Xilinx ISE tool.

WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip

The contemporary Network on Chips (NoCs) are becoming intricate in design to serve the high throughput and low latency demands of multicore platforms. The complexity level of interconnect module makes it extremely difficult to ensure the functional correctness at the presilicon verification stage. Hence, post-silicon debug is performed on NoC as a necessary step to capture the escaped network design faults. The traditional store and forward trace-based debug methods encounter the problems of large trace buffer requirement and limited availability of trace communication bandwidth. These constraints become more stringent for short-lived network faults (misroute, packet drop, etc.), which demand more frequent trace collection for their detection. In this regard, we propose WiND, which is wireless-enabled NoC for post-silicon debug. WiND is a robust NoC debug framework that optimally uses the limited trace buffer space and can efficiently speed up the trace communication. The proposed method augments wireless interfaces (WIs) on top of the baseline wired NoC for validation purposes. The wireless medium is utilized for long-range test payload communication to reduce the volume of trace. The WIs are also used for high-speed interchip trace transfer. A modified router architecture is used to enable the trace collection, and to enhance the trace communication. WiND platform is examined with several synthetic and SPLASH-2 benchmark workloads, and compared with the traditional wired platform. An overall improvement of 15%–26% on fault detection and 27%–34% on path reconstruction in the case of different faults is observed for the same trace buffer size.

Efficient signal selection using supervised learning model for enhanced state restoration

AbstractThe post‐silicon validation and debug is the most important task in the contemporary integrated circuit design methodology. The vital problem prevailing in this system is that it has limited observability and controllability due to the minimum number of storage space in the trace buffer. This tends to select the signals prudently in order to maximize state reconstruction. In the reported works, to select and to restore the signals efficiently it is categorized into two types like low simulation with high‐quality technique and high simulation with low‐quality technique. In this work, a node‐based combinational gate signal selection algorithm is proposed based on machine learning method that maximizes the state restoration capability. A significant improvement (80%) has made to achieve adequate simulation time with the high‐quality associated with the state‐of‐the‐art of supplementary methods.

An Approach to Mathematically Correlate Timing of Transaction Activity Between Pre-silicon and Post-silicon Environment

Post-silicon validation is a major challenge due to finite controllability and observability of actual silicon and makes debug a complex task. The trace signals routed from CPUs and other sources are translated by sampling unit to time-stamped trace messages and stored in trace buffer. Time stamp generated is not the exact time at which event has occurred. Hence, trace data read from trace buffer in post-silicon environment is not accurate from debug perspective. This is corrected by finding the variable delay along with various paths observed between two viewpoints, one being the source at which the event occurs and the other being the destination where the event gets recorded. One method to achieve time accurate debug data is by correlating the time at which data transaction event occurs at the signal with the time at which the trace data for that particular transaction event gets time-stamped. The major advantage is the successful reconstruction of pre-silicon environment for that particular post-silicon environment and enabling data to be viewed on the fly.

Topological Ordering Signal Selection Technique for Internet of Things based on Combinational Gate for Visibility Enhancement

In modern System on Chip (SoC) design consist of intelligence of products, Internet of Things (IoT) based devices, mobile phones, laptops, servers etc. This shrinking market reduces the design automation validation process. Signal selection is the most effective and challenging technique in post-silicon validation and debug. The vital problem prevailing in this method is that it has limited observability and controllability due to the minimum number of storage space in the trace buffer. This tends to select the signals prudently in order to maximize the state reconstruction. To identify the trace signals, signal restoration is the extensive metric that has been used so far. Topology-based restoration method is proposed here to minimize the error detectionlatency which helps to select the trace signals with minimum error or even errorless. This method aid to detect more number of errors within limited number of clock cyclesthan the restoration only selection techniques.

Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays

High-level synthesis (HLS) has gained considerable traction over recent years, as it allows for faster development and verification of hardware accelerators than traditional RTL design. While HLS allows for most bugs to be caught during software verification, certain non-deterministic or data-dependent bugs still require debugging the actual hardware system during execution. Recent work has focused on techniques to allow designers to perform in-system debug of HLS circuits in the context of the original software code; however, like RTL debug, the user must still determine the root cause of a bug using small execution traces, with lengthy debug turns. In this work, we demonstrate techniques aimed at reducing the time HLS designers spend performing in-system debug. Our approaches consist of performing data dependency analysis to guide the user in selecting which variables are observed by the debug instrumentation, as well as an associated debug overlay that allows for rapid reconfiguration of the debug logic, enabling rapid switching of variable observation between debug iterations. In addition, our overlay provides additional debug capability, such as selective function tracing and conditional buffer freeze points. We explore the area overhead of these different overlay features, showing a basic overlay with only a 1.7% increase in area overhead from the baseline debug instrumentation, while a deluxe variant offers 2×--7× improvement in trace buffer memory utilization with conditional buffer freeze support.

Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection

Incorporating on-chip trace buffers (TBs) helps to overcome the limited observability by tracing selected signals during post-silicon validation. The effectiveness of TB-based techniques largely relies on selection of appropriate trace signals. For processor-based systems, the selection becomes relatively easier because important signals can be identified. However, for a general digital block in a complex system-on-chip, recognizing necessary trace signals becomes extremely challenging and requires a systematic approach. Previous research on trace signal selection has mainly focused on improving reconstruction of unknown signal values with the help of traced signals. Even though it serves as a good selection principle, an effective signal selection must consider other important factors such as error detection (ED) with the traced signals, which in turn assist in localization and root-cause discovery. Additionally, from practical point of view, the signal selection algorithm needs to cater to factors like routing congestion and minimizing routing wire length. The proposed methodology of signal selection attempts to combine these three crucial factors of signal selection: restoration of untraced signal states, ED with traced signals and routing considerations. The concurrent maximization of all these three parameters is difficult as they have conflicting preference of the candidate trace signals. Hence, the proposed signal selection approach presents a methodology of judiciously mixing the choices of these three objectives. Furthermore, the restored and traced signal states are analyzed for the purpose of error localization at the gate level for several design error models.

Enabling On-the-Fly Hardware Tracing of Data Reads in Multicores

Software debugging is one of the most challenging aspects of embedded system development due to growing hardware and software complexity, limited visibility of system components, and tightening time-to-market. To find software bugs faster, developers often rely on on-chip trace modules with large buffers to capture program execution traces with minimum interference with program execution. However, the high volumes of trace data and the high cost of trace modules limit the visibility into the system operation to short program segments. This article introduces a new hardware/software technique for capturing and filtering read data value traces in multicores that enables a complete reconstruction of parallel program execution. The proposed technique exploits tracking of data reads in data caches and cache coherence protocol states to minimize the number of trace messages streamed out of the target platform to the software debugger. The effectiveness of the proposed technique is determined by analyzing the required trace port bandwidth and trace buffer sizes as a function of the data cache size and the number of processor cores. The results show that the proposed technique significantly reduces the required trace port bandwidth, from 12.2 to 73.9 times, when compared to the Nexus-like read data value tracing, thus enabling continuous on-the-fly data tracing at modest hardware cost.

Enhancing Network-on-Chip Performance by Reusing Trace Buffers

Ensuring the functional correctness of networks-on-chip (NoCs) can be particularly challenging, and communication-centric debug methodologies have been widely used by engineers to validate NoC functionality during post-silicon validation. Design-for-debug structures, such as trace buffers and monitors, are usually inserted in such systems-on-chip to enhance signal visibility. However, this debug hardware becomes underutilized once the chip goes into production. While the size and organization of the router buffers directly impact network throughput, these buffers also dominate the on-chip router area. We propose a scheme augmented virtual channel (AugVC) to reuse trace buffers to augment router buffers, with the objective of improving the overall network performance. The experimental results for a 64-node mesh network show that our proposed approach can reduce latency by up to 38.25% for transpose traffic compared to a baseline design with reduced buffer sizes. We also propose an extension, output port directed virtual channel (ODVC), that uses a modified virtual channel assignment strategy, on the basis of the designated output port of a network packet. This strategy reduces the average packet latency and area of the router by 45% and 32.4%, respectively.

Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost

In this paper, a design for debug (DFD) method that reuses test resources is proposed to reduce the debug cost in post-silicon validation. With the proposed method, the trace buffer is shared for embedded cores to capture the signatures of each core concurrently by reusing a test access mechanism. In this case, the depth of the trace buffer allocated to the core is reconfigurable and variable according to debug scheme. The experimental results indicate that the proposed DFD significantly reduces the debug time when the trace buffer is shared by cores in various debug cases.

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug

The trigger circuitry is critical for trace-based post-silicon debug, which detects specified events or event sequences to initiate or stop the tracing. In this paper, we propose a resource efficient trigger design for the post-silicon debug which integrates several different detection schemes to improve the detect ability. The design reuses the trace buffer to store the trigger set for event detection or store the transitions of the generated finite state machine for event sequence detection, which converts the trigger detection into simple read operations to the trace buffer and equality matching operations. Simulation and emulation are both used to validate the usability of the design. In comparison with the prior trigger circuits with the same trigger width, the proposed method provides much more powerful detect ability and configurability for complicated trigger conditions, and needs lower area overhead.

Reusing Trace Buffers as Victim Caches

With the increasing complexity of modern systems-on-chip, the possibility of functional errors escaping design verification is growing. Postsilicon validation targets the discovery of these errors in early hardware prototypes. Due to limited visibility and observability, dedicated design-for-debug (DFD) hardware, such as trace buffers, is inserted to aid postsilicon validation. In spite of its benefit, such hardware incurs area overheads that impose size limitations. However, the effective overhead could be reduced if the area dedicated to DFD could be reused in-field. In this paper, we present a novel method for reusing an existing trace buffer as a victim cache of a processor to enhance the performance. The trace buffer storage space is reused for the victim cache with a small additional controller logic. Simultaneous multithreading allows further fine-grained control of the victim cache, which can be shared between the threads based on the requirements of the applications. We also propose and evaluate different approaches to partition the victim cache between threads. Experimental results on several benchmark applications and trace buffer configurations show that the proposed approach can enhance the average performance by up to 8.3% with a minimal area overhead.

Integrated and effective in-system debugging approach in FPGA circuits

This paper explores the new approaches for trace-based and In-system debugging of high level synthesis-generated hardware. The presented approach also exhibits the use of the Event Observability Ports (EOP) which provides the source level event observability in the hardware. To trace the events, the use of the independent trace buffers also known as Event Observability Buffers (EOB) is also discussed. The EOB has the signal that specifies the enabling the data storage and allows the storage decisions cycle-by-cycle which are to be made on the basis of EOB-by-EOB. The proposed approach also reveals the timing relationships of the captured events in the trace buffers. To recover the lost relationships among these events, we have introduced two methods in this paper. We also presented the demonstration and effectiveness of the trace strategy of an EOB.

Managing Trace Summaries to Minimize Stalls During Postsilicon Validation

On-chip trace buffers are increasingly being used for at-speed debug during postsilicon validation. The limited size of these buffers results in their frequent overflowing. In scenarios when such overflowing is not desirable, the chip is stalled, and the state data recorded in these buffers are transferred off-chip. Such frequent stalling significantly impedes efficient debugging. We propose a novel scheme to minimize the number of such stalls using a portion of the trace buffer to also store summaries of trace messages. We describe an overlapped trace buffer architecture that uses a reduced number of ports to capture tapered summaries where both detailed and summary versions of traces are stored simultaneously. We propose a simple hardware structure to generate two kinds of trace summaries— spatial and temporal —as specified by the validation engineer. We introduce a storage specification language that allows the validation engineer to unambiguously specify the information to be captured in these summaries to the debug hardware. We demonstrate that our proposal significantly reduces the number of stalls for off-chip transfer of captured traces in four bug scenarios that are representative of different classes of bugs encountered during postsilicon validation.

Trace Buffer Attack on the AES Cipher

Since the standardization of AES/Rijndael symmetric-key cipher by NIST in 2001, it gained widespread acceptance in various protocols and withstood intense scrutiny from the theoretical cryptanalysts. From the physical implementation point of view, however, AES remained vulnerable. Practical attacks on AES via fault injection, differential power analysis, scan-chain and cache-access timing have been demonstrated so far. In this paper, we propose a novel and effective attack, termed Trace Buffer Attack. Trace buffers are extensively used for post-silicon debug of integrated circuits. We identify the trace buffer as a source of information leakage. We first report the detailed process of trace buffer attack assuming that the register-transfer level (RTL) implementation is available. We further analyze the AES encryption algorithm and Rijndael’s key expansion algorithm, and illustrate that trace buffer attack is feasible without implementation (RTL) knowledge. Our experimental results show that trace buffer attack is capable of partially recovering the secret keys of different AES implementations.