WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip

Abstract

The contemporary Network on Chips (NoCs) are becoming intricate in design to serve the high throughput and low latency demands of multicore platforms. The complexity level of interconnect module makes it extremely difficult to ensure the functional correctness at the presilicon verification stage. Hence, post-silicon debug is performed on NoC as a necessary step to capture the escaped network design faults. The traditional store and forward trace-based debug methods encounter the problems of large trace buffer requirement and limited availability of trace communication bandwidth. These constraints become more stringent for short-lived network faults (misroute, packet drop, etc.), which demand more frequent trace collection for their detection. In this regard, we propose WiND, which is wireless-enabled NoC for post-silicon debug. WiND is a robust NoC debug framework that optimally uses the limited trace buffer space and can efficiently speed up the trace communication. The proposed method augments wireless interfaces (WIs) on top of the baseline wired NoC for validation purposes. The wireless medium is utilized for long-range test payload communication to reduce the volume of trace. The WIs are also used for high-speed interchip trace transfer. A modified router architecture is used to enable the trace collection, and to enhance the trace communication. WiND platform is examined with several synthetic and SPLASH-2 benchmark workloads, and compared with the traditional wired platform. An overall improvement of 15%–26% on fault detection and 27%–34% on path reconstruction in the case of different faults is observed for the same trace buffer size.