Average Total Power Consumption Research Articles

Packet Error Rate Analysis and Power Allocation for CC-HARQ Over Rayleigh Fading Channels

In this letter, a novel approach is developed to evaluate the average packet error rate (PER) for chase combining (CC) based hybrid automatic repeat request (HARQ) protocol over block Rayleigh fading channels for the long packet system. A simple approximated expression for the average PER at the high signal-to-noise ratio (SNR) region is further proposed. Based on the approximation, the optimal power allocation (OPA) scheme for CC-HARQ is studied. The closed-form optimal assignment solution at the high SNR is derived to minimize the average total power consumption under packet loss rate (PLR) and maximum number of transmission rounds constraints. Furthermore, the impact of transmission parameters on the OPA scheme is investigated. It is found that the ratios among the optimal power sequence just depend on the targeted PLR and the maximum number of transmission rounds.

Application-aware virtual paths insertion for NOCs

Network-on-chip (NoC) has rapidly become a promising alternative for complex system-on-chip architectures including recent multicore architectures. Additionally, optimizing NoC architectures with respect to different design objectives that are suitable for a particular application domain is crucial for achieving high-performance and energy-efficient customized solutions. Despite the fact that many researches have provided various solutions for different aspects of NoCs design, a comprehensive NoCs system solution has not emerged yet. This paper presents a novel methodology to provide a solution for complex on-chip communication problems to reduce power, latency and area overhead. Our proposed NoC communication architecture is based on setting up virtual source–destination paths between selected pairs of NoCs cores so that the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these virtual paths. In this scheme, the paths are constructed for an application based on its task-graph at the design time. After that, the run time scheduling mechanism is applied to improve the buffer management, virtual channel and switch allocation schemes and hence, the constructed paths are optimized dynamically. Moreover, in our design the router complexity and its overheads are reduced. Additionally, the suggested router has been implemented on Xilinx Virtex-5 FPGA family. The evaluation results captured by SPLASH-2 benchmark suite reveal that in comparison with the conventional NoC router, the proposed router takes 25% and 53% reduction in latency and energy, respectively besides 3.5% area overhead. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and total power consumption with negligible area overhead.

Design and Experiment of Test-Bed for Straw Compression Forming and Baling

In order to study the performance of packing, compression and baling and obtain the influence of working parameters on complete machine, a test-bed was developed based on the packing, compression and baling devices of baler. The measure system consists of IPC, sensors, a data acquisition card and a type of software programmed by using VC++. It can real-time collect, display, process and analyze the parameters and loads of the working parts. Wheat straws with 40% moisture content were used to carry on compression and baling experiments. The test results show that average total power consumption of the working parts, average force acting on the plunger and average force acting on the connecting rod is 3.44 kW, 873.5 N and 11965.8 N respectively when the straw feed rate is 0.8 kg/s and the compression frequency of the plunger is 75 strokes per minute. The bale density can reach up to 125 kg/m3.

Performance Analysis of Cooperative ARQ Scheme with Co-channel Interference

In this paper, the performance of cooperative decode-and-forward (DF) automatic-repeat-request (ARQ) scheme with co-channel interference is investigated in a long-term static Rayleigh fading environment. We assume that the relay node is impaired by M interferers and the destination node is impaired by N interferers. A closed-form expression for the outage probability of cooperative DF ARQ scheme with co-channel interference is derived. Then we analyze the average throughput of the scheme with co-channel interference and further derive that the average throughput is mainly influenced by the interferers at the destination node. The average total power consumption per information packet of cooperative DF ARQ scheme with co-channel interference is investigated and a closed-form expression is obtained for cooperative DF ARQ scheme with co-channel interference, in which the source and relay may use different transmission power level in different transmission time slots. The closed-form expression is valid for any maximum number of transmission time slots L allowed by the protocol and may play a key role in optimizing power allocation. Numerical and simulation results are presented to verify our analysis.

A Power-Aware Multi-Level Cache Organization Effective for Multi-Core Embedded Systems

Recent system design trends suggest multicore architecture for all computing platforms including distributed and embedded systems running real-time applications. Multilevel caches in a multicore system pose serious challenges as cache requires huge amount of energy to be operated and cache increases unpredictability due to its dynamic behavior. Bandwidth and synchronization problems are also critical design factors for distributed and embedded systems. In this work, we propose a based cache memory organization which is very effective for real-time distributed and embedded systems. Cache-level miss table holds information about the memory blocks that cause most level-1 cache (CL1) misses under normal execution. Proposed cache organization also includes private victim caches (VCs) to hold level-1 victim blocks and shared level-2 cache (CL2) to help synchronization. Proposed cache organization improves CL1 cache hits that decrease memory latency and total power consumption and improve predictability and bandwidth. We simulate an 4-core system with two-level caches using MPEG4, H.264/AVC, FFT, MI, and DFT workload. Experimental results show that the proposed miss table based cache organization helps reduce average memory latency and total power consumption by 31% and 38%, respectively, when compared with cache organization without miss table and victim caches.

Intelligent cloud home energy management system using household appliance priority based scheduling based on prediction of renewable energy capability

Recent advances in micro-grid and distributed renewable energy have facilitated more efficient home energy management systems. However, due to characteristics of renewable energy such as intermittent energy generation, home energy management systems are inefficient and the recent systems therefore cannot be successfully applied to existing home. Therefore, this paper proposes intelligent cloud home energy management system (iCHEMS), considering these issues. iCHEMS assigns dynamic priority to a household appliance according to the type of appliance and its current status. In accordance with the assigned priority, the use of household appliances is scheduled considering renewable energy capability. We implemented iCHEMS in the test bed and conducted an experiment to verify the efficiency of the proposed system. The results show that the proposed system reduces the average total power consumption by up to 7.3 percent.

Obstacle-Aware Clock-Tree Shaping During Placement

Traditional integrated circuit (IC) design flows optimize clock networks before signal-net routing are limited by the quality of register placement. Existing publications also reflect this bias and focus mostly on clock routing. The few known techniques for register placement exhibit significant limitations and do not account for recent progress in large-scale placement and obstacle-aware clock-network synthesis. In this paper, we integrate clock network synthesis within global placement by optimizing register locations. We propose: 1) obstacle-aware virtual clock-tree synthesis; 2) arboreal clock-net contraction force with virtual-node insertion, which can handle multiple clock domains and gated clocks; and 3) an obstacle-avoidance force (OAF). Our work is validated on large benchmarks with numerous macroblocks. Experimental results indicate that our software implementation, called Lopper, prunes clock-tree branches to reduce their length by 30.0%-36.6% and average total dynamic power consumption by 6.8%-11.6% versus conventional wirelength-driven approaches. SPICE-driven simulations show that our methods improve robustness of clock trees.

Operating modes and power considerations of microhollow cathode discharge devices with elongated trenches

Microhollow cathode discharge (MHCD) devices generate microplasmas with high electron densities and reactive species, making them a prospective hydrocarbon reforming technology. Here we report on the electrical phenomena resulting from MHCD devices with elongated trenches using argon at atmospheric pressure and room temperature. Devices that were 100 μm wide, 100 μm deep, and 1 cm long exhibited self-pulsing current during constant voltage DC power application ranging from 0 mA to 32 mA. The capacitances for MHCDs with trenches 25, 100, and 250 μm wide were estimated to be 68, 70, and 33 μF respectively. A current-limited DC supply prevented self-pulsing, and resulted in abnormal, normal, or negative differential resistance (NDR), i.e. hollow cathode, operating modes. The NDR state manifested at lower current limits and occurred when the microplasma in the trench was discontinuous. Simulations from a corresponding, empirically determined circuit model showed larger total average power consumption (including the ballast resistance) during pulsed inputs (5.61–31.08 W) in comparison to constant voltage inputs (<1 W). These findings advance the development of these MHCDs for microplasma reforming applications, providing insights into operational modes and power consumption estimates critical to understanding the overall efficiency in the context of a future microplasma reforming system.

Fair and Minimal Power Allocation in a Two-Hop Relay Network for QoS Support

In this paper, we consider a two-hop decode-and-forward relay network where relay nodes have heterogeneous channel conditions. We propose a new fair and minimal power allocation scheme where a relay node is selected to forward packets based on thresholds for channel conditions of relay nodes and the selected relay node uses an adaptive power control to meet a given data rate requirement. The individual threshold values of relay nodes are determined based on the following three criteria: i) the average amounts of power consumption at relay nodes are all equal, ii) given outage probability and data rate requirements are guaranteed to support quality of service (QoS), and iii) the average total power consumption at all relay nodes is minimized. To determine threshold values for relay nodes we first mathematically model the proposed scheme and derive the average power consumption of each relay node. We then formulate an optimization problem to determine the threshold values that satisfy the above-mentioned three criteria. To solve the optimization problem, we rigorously analyze the performance of the proposed scheme, and show that the threshold values can be uniquely determined. Numerical and simulation results are provided to demonstrate various properties and the benefits of the proposed scheme.

Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding

Large external memory bandwidth requirement leads to increased system power dissipation and cost in video coding application. Majority of the external memory traffic in video encoder is due to reference data accesses. We describe a lossy reference frame compression technique that can be used in video coding with minimal impact on quality while significantly reducing power and bandwidth requirement. The low cost transformless compression technique uses lossy reference for motion estimation to reduce memory traffic, and lossless reference for motion compensation (MC) to avoid drift. Thus, it is compatible with all existing video standards. We calculate the quantization error bound and show that by storing quantization error separately, bandwidth overhead due to MC can be reduced significantly. The technique meets key requirements specific to the video encode application. 24-39% reduction in peak bandwidth and 23-31% reduction in total average power consumption are observed for IBBP sequences.

Impulse-Based Scheme for Crystal-Less ULP Radios

This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 ¿W with a clock generator inaccuracy of only 1%.

CMOS EIGHT-TRANSISTOR MEMORY CELL FOR LOW-DYNAMIC-POWER HIGH-SPEED EMBEDDED SRAM

Embedded SRAM design with high noise margin between read and write, low power, low supply voltages, and high speed become essential features in VLSI embedded applications. The complete embedded SRAM design of self-timing synchronization is proposed based on the CMOS eight-transistor (8T-Cell) memory cell circuit. The cell is based on the traditional six-transistor (6T-Cell) cross-coupled invertors with the addition of two NMOS transistors for separate read buffer circuit. The read buffer structure is based on pre-charging the read bit-line during the low value of read clock and evaluating the read bit-line during the high value of read clock, thereby maintaining one active line per column and eliminating the use of traditional sense amplifier with all its synchronization schemes. The simulation results show that the embedded SRAM of size 128-bit × 128-bit is operating at a maximum frequency of 200 MHz for Write and Read clock cycles with 1.62 V power supply, and measures a total average power consumption of 22.60 mW. All simulation results were conducted on 0.18 μm TSMC single poly and three layers of metals measuring a cell area of 2.2 × 3.0 μ m 2. The circuit is not meant to replace the SRAM with 6T-Cell transistor structure; however, it is attractive for applications related to high density with automation road-map design, such as graphic and network processor chips. In these applications, memory sizes are introduced in many different irregular geometries and uses all over the chip with storage sizes less than 20 k-bit, in addition, it is susceptible to large substrate noise as well as large coupling wire routing.

Low-power gated and buffered clock network construction

We propose an efficient algorithm to construct a low-power zero-skew gated clock network, given the module locations and activity information. Unlike previous works, we consider masking logic insertion and buffer insertion simultaneously, and guarantee to yield a zero-skew clock tree. Both the logical and physical information of the modules are carefully taken into consideration when determining where masking logic should be inserted. We also account for the power overhead of the control signals so that the total average power consumption of the constructed zero-skew gated clock network can be minimized. To this end, we present a recursive approach to compute the effective switched capacitance of a general gated and buffered clock network, accounting for both the clock tree's and controller tree's switched capacitance. The power consumptions of the gated clock networks constructed by our algorithm are 20 to 36% lower than those reported in the best previous work in the literature.

An address-light, integrated MAC and routing protocol for wireless sensor networks

We propose an address-light, integrated MAC and routing protocol (abbreviated AIMRP) for wireless sensor networks (WSNs). Due to the broad spectrum of WSN applications, there is a need for protocol solutions optimized for specific application classes. AIMRP is proposed for WSNs deployed for detecting rare events which require prompt detection and response. AIMRP organizes the network into concentric tiers around the sink(s), and routes event reports by forwarding them from one tier to another, in the direction of (one of) the sink(s). AIMRP is address-light in that it does not employ unique per-node addressing, and integrated since the MAC control packets are also responsible for finding the next-hop node to relay the data, via an anycast query. For reducing the energy expenditure due to idle-listening, AIMRP provides a power-saving algorithm which requires absolutely no synchronization or information exchange. We evaluate AIMRP through analysis and simulations, and compare it with another MAC protocol proposed for WSNs, S-MAC. AIMRP outperforms S-MAC for event-detection applications, in terms of total average power consumption, while satisfying identical sensor-to-sink latency constraints

A Low Cost-Low Power Multichannel Pulse Height Analyzer for University Balloon and Rocket Experiments

A simple low cost-low power consumption multichannel pulse height analyzer has been designed and fabricated for balloon and rocket use. This analyzer was designed to be used in a balloon experiment with a directional neutron detector to search for solar neutrons with energies greater than 10 Mev. It can-operate in the temperature range of -30°C to +70°C and can withstand storage temperature from -50°C to +90°C. The input pulses are digitized by an analog to digital converter with a clock rate of 2 MC. The output of the PHTC is read out by a series binary converter and is transmitted by a single subcarrier channel (70 KC ± 15% deviation standard IRIG Band E) to the ground, where it can be stored on tape or directly stored in a laboratory pulse height analyzer memory unit. The dead time of the PHTC is approximately 64 μsec, but the bandwidth of the subcarrier limits the overall dead time to 600 μsec. The analyzer was designed as a 32-channel pulse height analyzer, but by adding a stage to the series binary converter it can be used as a 64, or 128-channel pulse height analyzer. The total average power consumption is approximately 330 mW. The analysis range is from 150 mV to 4.6 V with adjustable zero setting. An external anticoincidence input is provided. This work was supported by the National Aeronautics and Space Administration under Contract NASr-211.