Multilevel Inverter Topology Research Articles

Low-Cost Single-Source 17 Level Multilevel Inverter with Reduced Switch Count

Abstract This paper introduces an innovative multi-level inverter (MLI) topology operating with a single DC source. The proposed structure consists of a DC-DC rectifier (HFL), a switched capacitor (SC) unit and a Packaged U-Cell (PUC) module. The topology synthesizes 17 voltage levels at the output with only 10 power switches, offering low control complexity and high power efficiency. The high number of levels at the output voltage provides a high quality output voltage wave. A soft charging cell (SCC) is used to suppress impulsive charging currents in the switched capacitors. Experimental results show that SCC effectively suppresses impulsive currents in switched capacitors. The high frequency link (HFL) used to provide high voltage gain improves the cost efficiency of the system by reducing transformer sizes and costs. Simulation and experimental results show that the proposed topology achieves 96.92% efficiency, near sinusoidal current output and total harmonic distortion (THD) values between 4.99% and 1.23%. Moreover, with a low cost function (CF) value of 1.60, it is proven to offer a viable alternative for applications such as Renewable Energy Systems (RES) and Electric Vehicles (EVs). These findings demonstrate the applicability of the proposed MLI topology in these areas with low cost, high efficiency and quality power output.

An improved SPWM control approach with aid of ant lion optimization for minimizing the THD in multilevel inverters

This article presents an innovative asymmetric multilevel inverter (MLI) topology that outperforms conventional counterparts. The introduced topology presents a breakthrough in implementing power electronics control by maximizing specific levels while minimizing switching components. A cutting-edge control scheme for optimal operation of the cascaded half-bridge MLI is presented. The ant lion optimization (ALO) algorithm was implemented to optimize the switching control to reduce the total harmonic distortion (THD) and improve power quality. For verification, the performance and effectiveness of the ALO technique are assessed by comparing its results to those obtained using the simplified sinusoidal pulse width modulation (SSPWM) technique, genetic algorithm (GA), and particle swarm optimization (PSO) in existing literature. Simulation results verified the efficacy of ALO in finding the optimal parameters. The suggested method showcases a remarkable reduction in the THD compared to SSPWM. The quality of the resulting waveform was enhanced, and both filter size and cost were significantly reduced. To meet stringent IEEE standards, an LC filter has been designed with minimal size and proper requirements. Experimental results validation of the suggested scheme, using a dSPACE R&D controller board unequivocally, confirmed its robustness and effectiveness. This groundbreaking study not only introduces a superior asymmetric MLI topology but also validates its exceptional performance through comprehensive analysis and experimentation. The experimental waveforms showed good matching with the simulation outcomes. The findings hold immense promise for advancing the field of power system control and revolutionizing the designing and implementation of efficient and cost-effective inverter systems.

A reduced device symmetrical-asymmetrical multilevel inverter with self capacitor voltage balancing and reduced capacitor voltage ripple

ABSTRACT Multilevel Inverters (MLIs) have gained widespread acceptance in high-power conversion due to their distinctive features, including minimised harmonic distortion in the output and reduced voltage stress on power switches. Nevertheless, including numerous DC sources and switches in MLIs increases costs and system complexity. To address this challenge, this paper introduces a hybrid MLI topology featuring a reduced device count suitable for symmetrical and asymmetrical source configurations. The proposed hybrid MLI topology (PHMLIT) can produce a 9-level output voltage with a symmetrical configuration and 7- or 11-levels output voltage with an asymmetrical configuration. Moreover, the cascaded connection of the cells of the PHMLIT generates a broad range of voltage levels across the output. Additionally, a novel switching strategy is devised to minimise the size of the capacitor. The comparative analysis illustrates that the PHMLIT exhibits superior characteristics compared to conventional and recently developed topologies regarding the number of switches, DC sources, diodes, capacitors, and total blocking voltage (TBV). Finally, the feasibility of the PHMLIT is confirmed through various simulation and experimental tests.

High‐efficiency multilevel inverter topology with minimal switching devices for enhanced power quality and reduced losses

AbstractThe advent of multilevel inverters (MLIs) has brought significant advancements in their applications across industrial, residential, and renewable energy sectors, as they produce high‐quality output voltage that closely approximates a sinusoid in small voltage steps or levels, resulting in lower total harmonic distortion (THD) and reduced electromagnetic interference (EMI). However, the MLI topologies require more switching unidirectional/bidirectional semiconductor devices with high standing voltage, gate drivers, and complex control strategies while attaining higher voltage levels. From this perspective of reducing component count and gate drivers, the objective is to develop a new MLI topology that overcomes the drawbacks above. In this article, a novel MLI topology is introduced in symmetric and asymmetric configurations aiming to attain fewer power electronic devices for synthesizing more steps in the load voltage in contrast with conventional topologies. The idea behind the approach is coining the series connected voltage source, which imbibes bidirectional current flow with an additional voltage source for performing algebraic operation under asymmetrical modes of operation. The proposed topology uses minimal on‐state switching devices leading to a diminution of power loss and voltage drop. The suggested topology is optimized for a fewer number of power devices, an input DC supply, and auxiliary gate drivers to achieve a maximum voltage level in the load terminals. The suggested topology has been verified in SIMULINK and the laboratory prototype is constructed in line with the simulated response to demonstrate its performance suitable for real‐time applications.

Comparative analysis of different types of pulse width modulation techniques for multilevel inverters

Multilevel inverters have gained significant attention in recent years due to their ability to achieve higher voltage and lower harmonic distortion compared to conventional two-level inverters. Pulse width modulation (PWM) techniques play a crucial role in controlling multilevel inverters by generating the required switching signals for their power electronic devices. This paper presents a comprehensive comparative analysis of various PWM techniques employed in multilevel inverters, including sinusoidal pulse width modulation (SPWM), space vector pulse width modulation (SVPWM), carrier-based pulse width modulation (CBPWM), and selective harmonic elimination (SHEPWM). Each PWM technique's advantages, limitations, and suitability for different multilevel inverter topologies are discussed. Furthermore, recent advancements and hybrid PWM techniques are also examined to explore potential improvements in performance and efficiency. This paper aims to provide researchers, engineers, and practitioners with valuable insights into selecting the most appropriate PWM technique for their specific multilevel inverter applications, considering factors such as performance requirements, cost constraints, and ease of implementation.

Design and Simulation of Reduced Switch 31-Level Multilevel Inverter Topology for PV Application

Design and Simulation of Reduced Switch 31-Level Multilevel Inverter Topology for PV Application

Minimization of the circuit components with modified cascaded multilevel inverter topology

This article examines a modified multilevel inverter circuit that uses basic units connected in cascade. The suggested circuit can be used with an inverter that is symmetrical or asymmetric. The magnitude of the DC voltage source is determined using a variety of methods in order to generate a large number of voltage levels. For both symmetrical and asymmetrical configurations, the magnitude of two DC sources in basic units can be used. The DC voltage source's magnitude is the same for each unit in the symmetrical configuration. However, in an asymmetrical configuration, the value of the DC source for the fundamental units is inequitable, and their magnitudes are obtained using various techniques. Comparison study demonstrates that the suggested circuit requires minimum components, reduces power loss, and boosts inverter efficiency. Additionally, in comparison to modern topologies, the standing voltage across the switches is acceptable. To verify the effectiveness of the investigated topology, simulation results for 15, 17, 23, and 31-level inverters are analysed.

Power Quality Enhancement in Grid-Connected Solar PV Systems Using Adaptive Control and Multilevel Inverter Topologies Under Dynamic Grid Conditions

This paper introduces a control strategy that uses an integrator-based positive sequence estimator to improve the power quality of a grid-connected double-stage solar PV system. The control extracts positive sequence components from distorted and unbalanced grid voltages to calculate unit templates and grid reference currents during grid anomalies like distortion, unbalance, sag/swell, and DC offset. A feedforward term is introduced to the photovoltaic array to ensure rapid transient response, and the DC-link voltage is adaptively regulated to reduce the voltage source converter (VSC) losses during weak grid conditions. The paper compares the performance of two-level and three-level inverters in this system configuration, highlighting the differences in power quality improvement, harmonic reduction, and system efficiency under various grid disturbances and intermittent solar conditions. Simulation results, performed in MATLAB, validate the superior performance of the three-level inverter in terms of lower total harmonic distortion (THD) in grid currents, in compliance with IEEE standard 519, while demonstrating the satisfactory response of both inverter types during challenging grid conditions like intermittent solar irradiation, DC offset, voltage distortions, unbalance, and voltage sag/swell.

ANFIS-PSO-Based Optimization for THD Reduction in Cascaded Multilevel Inverter UPS Systems

Uninterruptible Power Supplies (UPSs) protect electronic equipment by delivering consistent power. Among the core components of a UPS is the inverter, which converts stored DC energy from batteries into AC power. This work focuses on a cascaded multilevel inverter topology for its ability to reduce voltage Total Harmonic Distortion (THD), which is essential for maintaining UPS efficiency and power quality. Using an ANFIS (Adaptive Neuro-Fuzzy Inference System) model, enhanced with the Particle Swarm Optimization (PSO) algorithm, the switching angles were optimized to minimize THD. This work focused on an online UPS with a seven-level inverter structure powered by three LifePo4 S17 batteries, with critical load levels (100%, 95%, 50%, 15%, and 5%) represented in 35 experimental cases. The experimental design allowed the ANFIS-PSO model to adapt to varying voltages, achieving robust THD reduction. The results demonstrated that this combination of ANFIS and PSO provided effective angle optimization, with a low standard deviation of 0.06 between the training and simulated %THD, highlighting the process’s accuracy. The analysis showed that, in most cases, the simulated THD values closely aligned with, or even improved upon, the calculated values, with discrepancies not exceeding 0.2%. These findings support the ANFIS-PSO model’s potential in enhancing power electronics applications, particularly in critical sectors like renewable energy and power transmission, where THD minimization is crucial.

A 31 L multilevel inverter topology with less switching devices for hybrid electric vehicle applications

In this article, a 12 switch 31 L multi-level inverter (MLI) is proposed with the benefits of least switching devices for electric vehicle applications. In most electric vehicles (EV), conventional inverters are utilized so the lifetime of electric vehicle induction motors is reduced due to the high THD level and high voltage stress. To rectify this, a new inverter topology is proposed with minimum switching devices by increasing the level to 31, and also the THD should be maintained within IEEE standards. This inverter topology is constructed with variable DC sources (PV system) along with required capacitors and a polarity changer. The specific feature of this topology is that it can generate any level of voltage with minimum switching devices, less voltage stress, minimum THD, and less cost are tabulated in the comparison. This type of inverter can also applicable for high voltage (HV) applications and grid-connected systems. Furthermore, the proposed topology is simulated with MATLAB software and the downscale prototype model is developed using the DSPIC30f2010 controller.

A Novel Common‐Ground Switched‐Capacitor Type Dual‐Mode Five‐Level Transformer‐Less Multilevel Inverter

ABSTRACTThis paper presents a novel single‐source common‐ground switched‐capacitor (CGSC) type dual‐mode five‐level (5L) transformer‐less (TL) multilevel inverter (MLI) topology with inherent boosting capability. The proposed topology comprises a single DC source, nine power switches, and two capacitors with self‐voltage balancing ability, reducing the inverter's size, cost, and complexity. The direct connection of the negative terminal of the source to the neutral point of the load eliminates the leakage current. The converter can operate in both buck and boost mode based on the series–parallel switching conversion of the involved switches. The circuit description, control strategy, and design guidelines are discussed in detail. The steady‐state and dynamic performance of the proposed circuit is validated using MATLAB Simulink software. Reliability analysis of the proposed converter is done in detail. Furthermore, the proposed converter is being compared with state‐of‐the‐art topologies.

Enhancing Reliability in Multilevel Inverter: A Fault‐Tolerant Approach With Reduced Switch Count

ABSTRACTReliability is a major concern in multilevel inverters (MLI) due to the increased number of power switches and diodes, which increases the chance of switch failures and complicates the inverter design. The primary challenges faced by the current MLI design include higher control complexity, increased parasitic elements, more extensive protection, and lack of multiple fault tolerance. Therefore, developing reduced switch MLI with fault‐tolerant ability is crucial to ensure system availability and prevent adverse outcomes. To address these challenges, this article introduces a highly resilient fault‐tolerant reduced switch count (FTRSC) MLI topology offering fault tolerance with minimal switch count. The proposed topology provides fault tolerance in case of single‐ and multiple‐switch open‐circuit (OC) failures. The inherent fault‐tolerant operation is analyzed for the proposed topology's symmetric and asymmetric configurations. The simulation and experimental results validate the effectiveness of the proposed topology considering normal, faulty, and postfault conditions. Furthermore, the reliability evaluation of the proposed work is carried out using the Markov chain model, resulting in a high total mean time to failure of approximately 117,550 h/failures, along with an efficiency of 96.3%. These findings demonstrate that the proposed circuit has enhanced reliability and extended mean time to failure, affirming its suitability for sensitive industrial applications. Finally, a thorough comparison with recent studies highlights the superiority of the proposed system.

Traditional and Hybrid Topologies for Single-/Three-Phase Transformerless Multilevel Inverters

With increasing interest in integrating solar power into the utility grid, multilevel inverters are gaining much more attention for medium- and high-power applications due to their high-quality waveform, low voltage stress across active components, and low total harmonic distortion in output voltage. However, to achieve these benefits, a large number of active and passive components are required. A transformer is also required to provide galvanic isolation, which increases its size and weight and reduces its power density and efficiency. In order to overcome the disadvantages posed by transformer-based inverters, research is being conducted on the transformerless topology of multilevel inverters. The first aim of this review article is to summarize traditional transformerless multilevel inverters (TMLIs) considering both single- and three-phase topologies. Secondly, the main aim of this article is to provide a detailed overview of the hybrid topologies of TMLIs that employ fewer components for photovoltaic applications. In addition, this study compares traditional and hybrid single-/three-phase topologies in terms of component count and performance factors, which will be useful to researchers.

Review of recent trends of advancements in multilevel inverter topologies with reduced power switches and control techniques

AbstractCurrently, multilevel inverters (MLI) are comprehensively used to integrate renewable energy sources with the grid or high‐power applications. MLI has outstanding properties such as high‐level output voltage with tremendous power quality and negligible harmonics distortion. General MLI topologies have a more complex circuit, high overall cost and installation area. Due to a large number of power switches and isolation of control circuit, fewer power electronic switches and DC source along with its suitable control logic is the need of the hour. Therefore, a lot of research scope exists in this area. Here, some of the topologies with a fewer number of power switches are reviewed and scrutinized. An extensive analysis of the topologies, control strategy and applications are presented here, suggesting suitable multilevel inverter solutions to the known industrial application or new research.

Open-Circuit Fault-Tolerant High-Gain Multilevel Inverter Topology With Minimum of 2/3 Level in Postfault Condition

Open-Circuit Fault-Tolerant High-Gain Multilevel Inverter Topology With Minimum of 2/3 Level in Postfault Condition

Multi-level Inverter Topologies for Electric Vehicles with Voltages Higher than 800 V

Multi-level Inverter Topologies for Electric Vehicles with Voltages Higher than 800 V

An innovative 11-level multilevel inverter topology with rotating trapezoidal SPWM for industrial and renewable applications

This paper provides a new, less complex multilevel inverter topology that can be used for industrial loads and renewable energy sources. The arrangement consists of eight switches to produce an 11-level output voltage with two uneven input sources. Moreover, it can be connected in a cascade to increase the output voltage and number of levels even further. Due to its control mechanism, which is based on the Rotating Trapezoidal Sinusoidal Pulse Width Modulation control method for creating a high-quality output voltage, the inverter’s key characteristic is its very low harmonic distortion of 3.45% at the output voltage when compared to the advanced triangular carrier-based PWM techniques of phase disposition sinusoidal pulse width modulation (PD-SPWM) it produces harmonic distortion of 11.38% at the output voltage, phase opposition disposition sinusoidal pulse width modulation (POD-SPWM) it produces harmonic distortion of 6.43% at the output voltage, alternative phase opposition disposition sinusoidal pulse width modulation (APOD-SPWM) it produces harmonic distortion of 6.69% at the output voltage, IN-Shift sinusoidal pulse width modulation (IN-shift SPWM) it produces harmonic distortion of 3.93% at the output voltage. This inverter is commonly used in wind turbines and solar cells. The schemes are implemented in MATLAB/SIMULINK and are validated with single-phase 11-level inverter implemented by using digital signal controller (DSC).

Reduced switch single source multilevel inverter topology for renewable photovoltaic system applications

Reduced switch single source multilevel inverter topology for renewable photovoltaic system applications

Machine learning based fault detection technique for hybrid multi level inverter topology

AbstractMultilevel inverters (MLIs) have a significant contribution in many industrial sectors due to their improved power quality and lesser voltage stress, over the conventional three‐level inverters. However, the implementation of MLIs with an increased device count creates the scope of development in MLIs topologies. In this regard, a hybrid MLI topology is studied in this paper whose architecture is based on conventional two‐level inverters. This topology has lesser device count characteristics when compared to conventional and most of the recently presented configurations for nine‐level output voltage generation. The major issue of capacitor voltage balancing is resolved by employing an appropriate switching strategy. However, the semiconductor switches are the most vulnerable components and causes the open circuit faults frequently that creates issues in real time operation. Hence, it is important to detect the open circuit fault in switches in the least possible time. A new approach to open circuit fault detection technique based on the analysis of load voltage waveform is proposed in this paper. The wavelet transform technique has been implemented for feature extraction of load voltage. Later, the classification of the fault has been achieved by training an artificial neural network (ANN). The proposed work has been studied in MATLAB/simulation and the obtained results are verified experimentally.

A level shift carrier based SPWM for reduced switch 5-level multilevel inverter topology

A level shift carrier based SPWM for reduced switch 5-level multilevel inverter topology