Inverter Topology Research Articles

Control and Implementation of the Parallel Enhanced Commutation Integrated Nested Multilevel Inverter Topology

Due to their high efficiency and advanced battery management capability, cascaded multilevel inverters are an exciting option for battery electric powertrains. A promising, new and highly efficient cascaded multilevel inverter is the Parallel Enhanced Commutation Integrated Nested Multilevel Inverter. The inverter, with four semiconductor switches per submodule, can reconfigure individual battery cells in series and parallel and generate positive and negative phase voltages in regular four-quadrant operation. Therefore, emerging degrees of freedom in battery management and inverter operation must be managed and mapped into a specific Switching State for every switch. As controlling the high number of switches is safety-relevant, this publication profoundly explains the inverter’s functionality. We introduce a Switching Function that accepts easy-to-understand functional states as input, simplifying research on higher-level control algorithms and advanced single-cell battery-management capabilities. As the Switching Function guarantees safe operation and the correct contribution of every cell to the overall functionality of the inverter, it enables researchers to confidently use and thereby accelerate research on the promising new topology. The method we describe is fast, simple, deterministic and designed to convert setpoint specifications into an executable Switching Pattern. We prove that our Switching Function is operable on an FPGA with a twenty-kilohertz setpoint update operating a 17-level inverter.

A Comprehensive Review of Distributed MPPT for Grid-Tied PV Systems at the Sub-Module Level

Energy crises and the growth of the energy demand have increased the interest in utilizing unconventional power sources. Thus, renewable energy sources have become a topic of interest to mitigate rising energy concerns and cope with increased electricity demand. With remarkable merits including cleanness and abundance, photovoltaic (PV) solar energy systems are a key to solving these issues. The employed inverters should effectively utilize the maximum available power from the PV solar system and transfer this power to the utility grid without posing any further limitations. However, the unequal power generation of different PV systems caused by partial shading (PS) and other PV panel degradation factors leads to a reduction in generation capacity. One of the relatively new solutions to mitigate the mismatch concerns between the PV modules and sub-modules is to extract the maximum power of each sub-module individually. The main objective of this paper is to present a comprehensive review of such PV grid-connected inverters topologies associated with sub-module connection and control. It will classify the PV grid-tied inverters in accordance with the level where the maximum power point tracking (MPPT) system is implemented. A special focus has been placed on sub-module microinverters (MI) in terms of circuit topologies, conversion efficiency, and controller design. This paper provides a comprehensive analysis of employing the distributed MPPT (DMPPT) approach to maximize the power generation of PV systems by mitigating the mismatch issues inside the PV module. The circuit topology, PV system configuration, and MPPT algorithms used for applying DMPPT solutions in PV SMs are discussed in detail in this study.

A Single-Stage Closed Loop Control of SC-Based Inverter

This work presents a closed loop five-Level grid-connected inverter. The inverter is based on the switched capacitor approach. The suggested architecture has a lower number of components and is able to maintain a voltage balance across the various capacitors in the system. The construction that has been presented offers a number of benefits, including the capacity to produce five-level voltage output, lower current THD, and enhanced efficiency. Additionally, leakage-current in the circuit is eliminated due to the common grounding configuration. The current injected into the grid is controlled by a PI controller. As a result, a carefully controlled current of the desired quality can be injected into the system using just one renewable energy source. In order to test the suggested topology, the level-shifted sinusoidal pulse width modulation scheme is adopted. The design of switched capacitors as well as the computation of power loss in switches is offered. The performance of this suggested inverter topology is evaluated in comparison to other topologies that are recently presented in the literature. In addition, the power losses and efficiency are calculated using thermal modeling of the topology in PLECS software. MATLAB-2018/Simulink is used to simulate and analyze the PV-connected grid system.

A Survey on the State-of-the-Art and Future Trends of Multilevel Inverters in BEVs

All electric vehicles are the only way to decarbonize transport quickly and substantially. Although multilevel inverters have already been used in some transportation modes, they are rarely used in road transportation, especially in light-duty passenger BEVs. With the transition to a high 800-V DC link to extend the driving range and enable extreme fast charging, the possibility of using multilevel inverters in commercial light-duty passenger BEVs becomes feasible. Higher efficiency, higher power density, better waveform quality, lower switching frequency, the possibility of using low-rated switches, and inherent fault tolerance are known advantages of multilevel inverters that make them an efficient option for replacing 2-level inverters in high DC link passenger BEVs. This paper discusses high DC link voltage benefits in light-duty passenger BEVs, presents the state-of-the-art of different conventional multilevel inverter topologies used in BEVs, and compares them with conventional 2-level inverters from different aspects and limitations. Based on commercial upper-class passengers’ BEV data and a review of multilevel inverters on the market, future trends and possible research areas are identified.

A Reduced Switch Count Seven-Level Boost ANPC Based Grid Following Inverter Topology With Photovoltaic Integration

A boost active-neutral-point-clamped (BANPC) multilevel inverter based on a switched-capacitor network generally shows a bargain between the number of switches and its voltage rating. Moreover, control complexities are increased with the increase in switch count. In this paper, a new single-phase seven-level boosted ANPC (7L-BANPC) topology using 8(eight) switches, one floating capacitor, and one dc source is presented. The proposed inverter is capable of producing 1.5 times voltage boosting and needs a lower switch voltage rating. The efficiency of the proposed inverter is increased significantly due to lower rating switching devices and a reduced number of total conducting switches. The unipolar level-shifted sine pulse width modulation is considered for controlling the proposed inverter. A three-phase single-stage grid-connected SPV system with the proposed 7L-BANPC inverter is implemented. For the proposed system, theoretical analysis and design calculations are illustrated. The steady-state and dynamic performances of the proposed inverter as well as the grid-connected SPV system under different load power factors, modulation indices, and environmental conditions are simulated using the MATLAB/Simulink software and tested using OPAL-RT real-time emulator. A comparison with existing topologies clearly shows the benefits of the proposed inverter.

Modulated Model Predictive Torque Control for Fault-Tolerant Inverter-Fed Induction Motor Drives With Single DC-Link Voltage Sensor

Four-switch three-phase inverter (FSTPI) is widely used as a cost-effective fault-tolerant topology of six-switch three-phase inverter with an open-phase fault. To solve the inherent dc-link capacitor voltage offset (CVO) issue of FSTPI, two dc-link capacitor voltage sensors are required in conventional model predictive torque control (MPTC) strategies. To improve the reliability and reduce the cost of induction motor (IM) drives, a modulated MPTC (M-MPTC) for FSTPI-fed IM with single dc-link voltage sensor is proposed in this article. Therein, the relationship of the CVO and the load current is established to obtain the fundamental component of CVO. The two capacitor voltages are reconstructed by single dc-link voltage sensor and the fundamental component of CVO. To suppress the CVO, a cost function that only contains the output voltage vector is designed. The inner relationship between the proposed M-MPTC with single dc-link voltage sensor and the conventional M-MPTC with two dc-link voltage sensors is derived. To retain the load current within the allowed range, a current constraint scheme is proposed and integrated into the M-MPTC. Various simulation and experimental studies are carried out to verify the effectiveness of the proposed strategy.

Three-Phase Multiport DC–AC Inverter for Interfacing Photovoltaic and Energy Storage Systems to the Electric Grid

Distributed renewable energy sources (RES) in combination with hybrid energy storage systems are capable to smooth electric power supply and provide ancillary services to the electric grid. In such applications, multiple separate DC-DC and DC-AC converters are utilized, which are configured in complex and costly architectures. In this paper, a new non-isolated multiport DC-AC power inverter is presented, which comprises less passive components and less high-frequency power semiconductors. The proposed grid-connected multiport converter (MPC) enables the integrated power management of a photovoltaic (PV) array, a battery unit, a supercapacitor bank and the battery of an electric vehicle. The power circuit of the proposed MPC inverter is based on a new version of a split-source inverter topology to support bidirectional power flow and enables to connect the PV source directly to the DC-link. The proposed design is accompanied by a specifically developed control method which enables to implement the maximum power point tracking (MPPT) process without the need of any extra power converter, regulate the power flow at each port independently, as well as to control the power flow between its ports. An experimental prototype of the proposed MPC inverter has been constructed and its operation has been validated experimentally under various power flow scenarios.

DC-Side Soft-Switching Inverter With Modified Space-Vector Modulation Scheme

Three-phase soft-switching inverters are promising in order to reduce the losses in the switching devices and to reduce the electromagnetic interference produced by severe di/dt and dv/dt, which enables the operation of the inverter at higher switching frequency. This work proposes a DC-side three-phase zero-voltage soft-switching inverter topology that can be sub-categorized under actively clamped resonant dc-link topologies. Moreover, a modified space-vector modulation scheme is proposed, such that all the devices operate under zero-voltage switching condition. Compared to other similar dc-link soft-switching topologies, the proposed topology does not require feedback from the inverter output currents to achieve soft-switching operation. Unlike conventional space-vector modulation techniques, the proposed modified space-vector modulation does not require to turn-on the top and/or the bottom three switches of the two-level inverter at the same time to implement the zero vectors, which allows a reduction of the effective commutating time of the two-level inverter switches by one-third, during a grid voltage cycle. The auxiliary capacitor is only charged to a fraction of the dc bus voltage. Simulation and experimental results on a 10-kW and 100-kHz switching frequency lab-scale prototype are presented to demonstrate the validity and effectiveness of the proposed zero-voltage switching topology and modulation scheme on reducing the switching losses and electromagnetic interference.

Design and Analysis of a Novel Multi-Level Inverter Topology Using DC Sources

Design and Analysis of a Novel Multi-Level Inverter Topology Using DC Sources

Design and Implementation of Three Phase TCHB-Based DVR

This article presents the design of a reduced device count and enhanced compensation capability 5-level transistor clamped H-bridge (TCHB) inverter topology based DVR in a three phase system. TCHB-based DVR is designed for the prototype distribution system. The improved performance of the DVR is observed due to the implementation of the TCHB inverter. The unit vector template based PI controller is used for DVR implementation. The developed DVR is used to eliminate the various power quality disturbances (PQD) such as the sag, voltage imbalance, voltage harmonics, and voltage swell for the three phase system. Compensation capability of the developed DVR is demonstrated through simulation and experimentation. The developed DVR is working effectively by mitigating power quality disturbances with reduced filter size and switching frequency in comparison with existing 2-level topologies. This topology requires only one DC source as compared to CHB MLI. The grid is operated at 110 V/phase and 1.5 kVA/phase rating and DVR is designed for 55 VA/phase rating.

Investigation of efficient multilevel inverter for photovoltaic energy system and electric vehicle applications

Introduction. This research presents a simple single-phase pulse-width modulated 7-level inverter topology for renewable system which allows home-grid applications with electric vehicle charging. Although multilevel inverters have appealing qualities, their vast range of application is limited by the use of more switches in the traditional arrangement. As a result, a novel symmetrical 7-level inverter is proposed, which has the fewest number of unidirectional switches with gate circuits, providing the lowest switching losses, conduction losses, total harmonic distortion and higher efficiency than conventional topology. The novelty of the proposed work consists of a novel modular inverter structure for photovoltaic energy system and electric vehicle applications with fewer numbers of switches and compact in size. Purpose. The proposed system aims to reduce switch count, overall harmonic distortions, and power loss. There are no passive filters required, and the constituted optimizes power quality by producing distortion-free sinusoidal output voltage as the level count increases while reducing power losses. Methods. The proposed topology is implemented with MATLAB/Simulink, using gating pulses and various pulse-width modulation methodologies. Moreover, the proposed model also has been validated and compared to the hardware system. Results. Total harmonic distortion, number of power switches, output voltage, current, power losses and number of DC sources are investigated with conventional topology. Practical value. The proposed topology has proven to be extremely beneficial for implementing photovoltaic-based stand-alone multilevel inverter and electric vehicle charging applications.

Cavitation Detection in a Tonpilz-Type Transducer for Active SONAR Transmission System

The active sound navigation and ranging (SONAR) transmission system emits acoustic pulses underwater using a wave generator, a SONAR power amplifier (SPA), and a projector. The acoustic pulse travel in the direction of the target and return as an echo to a hydrophone to learn the range or speed of the object. Often the same device is used as a hydrophone and a projector; in this context, it is known as a transducer. In order to obtain a maximum range of detection in the SONAR, it is desirable to generate the maximum amount of acoustic power until the point in which the echo can be detectable in an atmosphere with non-wished noise. Therefore, a high value of source level (SL) is required that depends largely on the value of electrical power applied to the transducer (Pe). However, when trying to obtain the maximum range of detection in the SONAR system there are the following three peculiar limitations that affect performance: The cavitation, the reverberation, and the effect of interaction in the near field. In this paper, an experimental measurement methodology is presented to detect the cavitation effects in a tonpilz-type transducer for an active SONAR transmission system using a transducer as a projector and a calibrated hydrophone in a hydroacoustic tank by measuring the parameters of total harmonic distortion of the fundamental waveform (THD-F) of the generated acoustic pulse, transmitting voltage response (TVR) to characterize the system and sound pressure level (SPL) that indicates the intensity of sound at a given distance. Whereas the reverberation and the interaction effect in the near field are objects of other study cases. A 570.21 W and THD-F < 5% switched-mode power amplifier (SMPA) prototype was developed to excite the electroacoustic transducer employing a full-bridge inverter (FBI) topology and a digital controller using a field-programmable gate array (FPGA) for unipolar sine pulse width modulation (SPWM) to generate a continuous wave (CW) acoustic pulse at a frequency 11.6 kHz. The results obtained show that from the level of Pe=196.05 W with the transducer at 1 m of depth, the value of THD-F increases significantly while the behavior of the TVR and SPL parameters is affected since it is not as expected and is attributed when cavitation occurs.

Student Project-Based Space Vector Modulation Technique for Power Electronics Laboratory

Two-level DC/AC inverter topologies are widely used for low voltage and high voltage applications in power systems and industrial areas. Space Vector Modulation (SVM) is a popular Pulse-Width Modulation technique used for controlling the inverters and providing the efficient energy conversion from DC sources. However, applications of SVM-based studies are limited in the Power Electronics Laboratory (PEL) due to the vital risks associated with high voltage applications, and it is not easily learned through mathematical analysis and visual learning without implementation by undergraduate students. A simulation and experimental setup of an SVM-controlled two-level, three-phase inverter was presented in this study for undergraduate students to learn its basics in the PEL. Several programs were used to simulate the inverter in the classroom environment and to design a power circuit and microcontroller-based printed circuit board of the inverter for PEL experiments. The two case studies were given. In the case results, the output voltage waveforms of simulation and experimental inverters were compared to show the validation of simulation results. With this study, the students’ experience is enhanced in electronic circuit design, programming, coordination with hardware and software development activities, self-learning, and teamwork. Additionally, practical applications increase undergraduate students’ interest in Power Electronics Courses and reinforce their knowledge from lecture and laboratory studies.

Radiation study on the parallel topology of SiC MOSFET and Si IGBT inverter

The electromagnetic radiation interference mechanism from multiple noise sources on the parallel topology of SiC MOSFET and Si IGBT Inverter is blurred, which will seriously affect the high reliability application of the structure. In order to solve this problem, a topological radiation EMI prediction method is proposed, the method includes the establishment of radiation equivalent models and radiation guidelines, the proposed inverter parallel topology radiation. The modeling method of electromagnetic interference can effectively analyze the influence of radiation interference of SiC and Si devices coupled with each other, and the established PCB radiation near and far field simulation can effectively realize the accurate prediction of radiation interference of inverter parallel topology, and finally the experimental platform of the parallel SiC MOSFET and Si IGBT inverter is built and tested, the test results demonstrate the accuracy of the proposed method.

Switched capacitor-based quadruple boost multilevel inverter topology with reduced switch count and its extension

ABSTRACT Power converters enhance the DC-AC power supply by using multi-level inverters based on switched capacitor technology. The voltage stress on the switches in switched capacitor-based multi-level inverters decreases as the number of switches rises, and vice versa when the number of switches falls. This paper suggests a quadruple boost nine-level inverter based on a switched capacitor with a single voltage source to address this issue. Only nine switches are used in the suggested architecture to implement the inverter with two diodes and two capacitors. Since the diodes and capacitors are linked to the low voltage input side, the total voltage stress of the inverter is kept low even at the elevated for quadruple boost output voltage. The theoretical study, computations, and design parameters of the nine-level inverter are presented in this paper. The switching specifics of the seven-level boost extension topology are also reported in this work. Simulations and laboratory tests on a 120 W inverter prototype have confirmed the viability of the suggested topology.

Design and analysis of a new multi-level inverter topology with a reduced number of switches and controlled by PDPWM technique

With their many advantages, including low power dissipation in power switches, low harmonic content, and reduced electromagnetic interference (EMI) from the inverter, multilevel converter (MLI) topologies are becoming more and more in demand in high and medium power applications. This paper introduces a novel multi-level symmetric inverter topology with adopted control. The objectives of this article are to architecturally define the positions of the various switches, to choose the right switches and to propose an inverter control strategy that will eliminate harmonics while producing the ideal output voltage/current. By using fewer switching elements, fewer voltage sources, and switches with a total harmonic content (THD) which reduces losses and a drop in minimum voltage (Vstrssj), the proposed topology is more efficient than conventional inverters with the same number of levels. The new topology will be demonstrated using a seven-level single-phase inverter. For various modulation indices, MATLAB-SIMULINK is used to study and validate the topology.

Reliability Assessment of Power Semiconductor Devices for a 13-Level Boost Inverter Topology

Since the last few decades, research on multilevel inverters (MLIs) has been growing in the power electronics field. The MLI is preferred over conventional two-level converters due to its improved performance. In recent years, different types of MLI architectures have been proposed, each employing a unique combination of power semiconductor devices to produce a multilevel output voltage waveform. The reliability of a multilevel inverter is a crucial performance indicator that must be taken into account at every stage from design to commercialization. MLI is vulnerable to a variety of failure modes and processes due to a large number of interdependent components. In this paper, a 13-level boost inverter topology has been analyzed and test results are presented and discussed. The analysis has been carried out in terms of open-circuit fault (OCF), short-circuit fault (SCF), power loss, and thermal analysis. The results have been discussed and recommendations have been made for the better design of the inverter topology to improve reliability.

Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting Qubit Readout

This article proposes a cryogenic inverter-based low noise amplifier (LNA) for qubit readout. Its input impedance matching is realized by a high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> on-chip gate inductor and capacitive load through the gate-to-drain feedback capacitance of the input transistors. Cascode transistors are used to optimize the impedance matching, which results in a larger gate inductor and smaller load capacitor and hence a higher passive and inverter gain. Owing to the high passive gain and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factor of the gate inductor at 4 K, the noise of the active stages is substantially suppressed with a negligible noise contribution of the gate inductor. Moreover, with the current re-use in the inverter topology, less power consumption is achieved for the given transconductance of transistors. The input impedance, gain, and noise analyses of the proposed LNA are performed for room temperature (RT) operation, and its noise optimization is done by taking the cryogenic operation of the devices into account. We demonstrate with the circuit analysis and measurement results that the input impedance of the LNA has a low sensitivity to variations on device parameters at cryogenic temperatures. The LNA is implemented in a 28 nm CMOS technology. It achieves 0.4–0.7 dB noise figure (NF) with 4.2 mW power consumption at 4 K, and its operating frequency is between 6–8 GHz. The LNA consumes very low power compared to the state-of-the-art cryogenic CMOS LNAs while providing similar NF performance at 4 K, which makes it suitable for dilution refrigerators.

High Boost Seventeen-Level Switched Capacitor Inverter Topology With Continuous Input Current

High Boost Seventeen-Level Switched Capacitor Inverter Topology With Continuous Input Current

An Advanced Switched-Capacitor Multilevel Inverter Topology With a Robust PWM Controlling Technique and Voltage Boosting Property for the Grid-Connected Renewable Energy Applications

This paper proposes an improved switched-capacitor Multilevel Inverter that utilizes fewer components. The switched capacitors are employed with the DC sources in the proposed configuration to minimize the number of DC-Links in the structure, which keeps the structure compact and combinable. Those capacitors enjoy a self-charging susceptibility with the ability to balance naturally. The suggested structure supports the expansion process to catch up with satisfactory output power levels based on a slight increase in the components count. The targeted application for this inverter involves a renewable energy system (RES) to exploit the extracted electrical power and inject it into the grid. The paper suggests a developed PWM controller to control the system’s operation. The controlling scheme has the ability to adjust the balance in the DC-Links voltages to keep generating a regular output voltage. Furthermore, it helps in extracting the maximum available power from renewable resources. Meanwhile, the controller injects the real power component into the grid, which guarantees the unit power factor operation and enhances the grid’s performance. The simulation results for both sides of RES are carried out in MATLAB/Simulink, and these results are verified experimentally through the dSPACE-1103 hardware.