Logic Topology Research Articles

Hybrid Path Generation Method for Multi-Axis Laser Metal Deposition of Overhanging Thin-Walled Structures.

Additive manufacturing has advantages over other traditional manufacturing technologies for the fabrication of complex thin-walled parts. Previous correlation path strategies, when applied to laser metal deposition processes, suffer from contour deposition transboundary and surface "scar" type overstacking. Therefore, this paper proposes a hybrid path generation method for the laser metal deposition process. First, the topological logic of the STL model of the part is restored to reduce redundant calculations at the stage of obtaining the layered contour. Then, the path points are planned on the basis of the offset contours in a helical upward trend to form a globally continuous composite path in space considering the melt channel width. Finally, vectors that adaptively fit to the model surface are generated for the path points as tool orientations and they are optimized by smoothing the rotation angles. The results of experiments conducted on a multi-axis machine equipped with a laser metal deposition module show that the path generated by the proposed method is not only capable of thin-walled structures with overhanging and curved surface features but also improves the surface imperfections of the part due to sudden changes in the angle of rotation while ensuring the boundary dimensions.

Person re‐identification via deep compound eye network and pose repair module

AbstractPerson re‐identification is aimed at searching for specific target pedestrians from non‐intersecting cameras. However, in real complex scenes, pedestrians are easily obscured, which makes the target pedestrian search task time‐consuming and challenging. To address the problem of pedestrians' susceptibility to occlusion, a person re‐identification via deep compound eye network (CEN) and pose repair module is proposed, which includes (1) A deep CEN based on multi‐camera logical topology is proposed, which adopts graph convolution and a Gated Recurrent Unit to capture the temporal and spatial information of pedestrian walking and finally carries out pedestrian global matching through the Siamese network; (2) An integrated spatial‐temporal information aggregation network is designed to facilitate pose repair. The target pedestrian features under the multi‐level logic topology camera are utilised as auxiliary information to repair the occluded target pedestrian image, so as to reduce the impact of pedestrian mismatch due to pose changes; (3) A joint optimisation mechanism of CEN and pose repair network is introduced, where multi‐camera logical topology inference provides auxiliary information and retrieval order for the pose repair network. The authors conducted experiments on multiple datasets, including Occluded‐DukeMTMC, CUHK‐SYSU, PRW, SLP, and UJS‐reID. The results indicate that the authors’ method achieved significant performance across these datasets. Specifically, on the CUHK‐SYSU dataset, the authors’ model achieved a top‐1 accuracy of 89.1% and a mean Average Precision accuracy of 83.1% in the recognition of occluded individuals.

Dynamic Tangled Derivative Logic of Metric Spaces

Dynamical systems are abstract models of interaction between space and time. They are often used in fields such as physics and engineering to understand complex processes, but due to their general nature, they have found applications for studying computational processes, interaction in multi-agent systems, machine learning algorithms and other computer science related phenomena. In the vast majority of applications, a dynamical system consists of the action of a continuous `transition function' on a metric space. In this work, we consider decidable formal systems for reasoning about such structures. Spatial logics can be traced back to the 1940's, but our work follows a more dynamic turn that these logics have taken due to two recent developments: the study of the topological mu-calculus, and the the integration of linear temporal logic with logics based on the Cantor derivative. In this paper, we combine dynamic topological logics based on the Cantor derivative and the `next point in time' operators with an expressively complete fixed point operator to produce a combination of the topological mu-calculus with linear temporal logic. We show that the resulting logics are decidable and have a natural axiomatisation. Moreover, we prove that these logics are complete for interpretations on the Cantor space, the rational numbers, and subspaces thereof.

Ditch incorporated organic thin film transistor based organic all-p inverter: a novel approach

This paper demonstrates the static and dynamic characteristics of all-p organic inverter employing a bottom gate bottom contact organic thin film transistor with a ditch incorporated into the OSC and additional p+ doping done to its S/D nearing area. Various configurations of OTFT have been experimented with and it is found that as compared to an OTFT without extra p+ doping, the devices having additional doping show better responses. Where, for SG OTFT, ID is derived to be 18 μs, yet the one with extra doping illustrates a swooping 16.67% increased output current of 21 μs. To enhance the performance of the device further, a ditch of 30 nm, embedded 10 nm into the OSC is incorporated, further augmenting the performance of the device by 55.5% as compared to the conventional BGBC. Besides, the proposed inverter presents a considerably elevated performance in terms of robustness and low and high noise margins. This paper further compares the inverter using Diode Load Logic and Zero Vgs Load Logic topologies, wherein it was found that DLL shows an exceptional 211% less propagation delay τ p of 27 μs, as compared to 84 μs delay experienced by ZVLL. But comparing the two topologies in terms of the static response, ZVLL are way better and preferred over the counterparts since ZVLL configuration displays 20.5% augmented Noise Margin, improved gain, and overall robustness. Owing to the performance parameters achieved, such organic inverters may be incorporated into integrated circuits rendering trustworthiness to digital operations in electronic circuits and numerous cascading applications. Since the organic inverters made using the proposed OTFT exhibit a decent gain hence have an apparent prospective of driving myriad-stage logic like ring oscillators and memory blocks. Moreover, these may be employed in the areas of biosensors and wearable electronics as well wherever.

Predicting academic performance of learners with the three domains of learning data using neuro-fuzzy model and machine learning algorithms

In recent days, learners faced difficulties learning programming courses. This research study will help the learners learn complex concepts quickly with different activities like flipped classrooms, online quizzes, learning by doing, and a virtual laboratory. This research is carried out to address the difficulties of learners and cover all the domains of learning, including knowledge, Skill, and Attitude. The fuzzy logic method has recently been applied in education to overcome these restrictions. While employing the fuzzy logic approach to evaluate student achievement, qualifications are assessed qualitatively rather than quantitatively. This research study applies Fuzzy Logic in the first stage, Factor Analysis (FA), and Machine Learning (ML) techniques in the second stage to discover essential factors associated with the effective use of Active Learning Strategies (ALS) in the Learning Management System (LMS) of information technology course learners. Fuzzy logic and neural network topology can be coupled using ANFIS, an adaptable network. FA is performed to find the critical factors for successful learners. The study compares the performance of five supervised machine learning algorithms: K-Nearest Neighbor, Decision Tree, Naive Bayes, Discriminant Analysis, and Support Vector Machine. These classifiers are evaluated to determine their suitability and model fit in the context of the research. In this study, real-time data is collected from B.Tech Information Technology learners. The following prediction models achieved high accuracy before FA analysis: Naive Bayes (90 %), Support Vector Machine (89 %), Discriminant Analysis (88 %), Decision Tree (86 %), and K-Nearest Neighbors (82 %). Naive Bayes gives the best accuracy, with 90 %. Following factor analysis (FA), the accuracy achieved by various classifiers is as follows: Naive Bayes - 92 %, K-Nearest Neighbors - 92 %, Support Vector Machine - 90 %, Discriminant Analysis - 89 %, and Decision Tree - 88 %. Among these, Naive Bayes and K-Nearest Neighbors exhibit the highest accuracy of 92 %.

Untangled: A Complete Dynamic Topological Logic

Dynamical systems are general models of change or movement over time with a broad area of applicability to many branches of science, including computer science and AI. Dynamic topological logic (DTL) is a formal framework for symbolic reasoning about dynamical systems. DTL can express various liveness and reachability conditions on such systems, but has the drawback that the only known axiomatisation requires an extended language. In this paper, we consider dynamic topological logic restricted to the class of scattered spaces. Scattered spaces appear in the context of computational logic as they provide semantics for provability and enjoy definable fixed points. We exhibit the first sound and complete dynamic topological logic in the original language of DTL. In particular, we show that the version of DTL based on the class of scattered spaces is finitely axiomatisable, and that the natural axiomatisation is sound and complete.

Logical Blocks for Fault-Tolerant Topological Quantum Computation

Logical gates constitute the building blocks of fault-tolerant quantum computation. While quantum error-corrected memories have been extensively studied in the literature, explicit constructions and detailed analyses of thresholds and resource overheads of universal logical gate sets have so far been limited. In this paper, we present a comprehensive framework for universal fault-tolerant logic motivated by the combined need for platform-independent logical gate definitions, flexible and scalable tools for numerical analysis, and exploration of novel schemes for universal logic that improve resource overheads. Central to our framework is the description of logical gates holistically in a way which treats space and time on a similar footing. Focusing on schemes based on surface codes, we introduce explicit, but platform-independent representations of topological logic gates -- called logical blocks -- and generate new, overhead-efficient methods for universal quantum computation. As a specific example, we propose fault-tolerant schemes based on surface codes concatenated with more general low-density parity check (LDPC) codes. The logical blocks framework enables a convenient mapping from an abstract description of the logical gate to a precise set of physical instructions for both circuit-based and fusion-based quantum computation (FBQC). Using this, we numerically simulate a surface-code-based universal gate set implemented with FBQC, and verify that their thresholds are consistent with the bulk memory threshold. We find that boundaries, defects, and twists can significantly impact the logical error rate scaling, with periodic boundary conditions potentially halving the resource requirements. Motivated by the favorable logical error rates for boundaryless computation, we introduce a novel computational scheme based on the teleportation of twists that may offer further resource reductions.

On piecewise hyperdefinable groups

The aim of this paper is to generalize and improve two of the main model-theoretic results of “Stable group theory and approximate subgroups” by Hrushovski to the context of piecewise hyperdefinable sets. The first one is the existence of Lie models. The second one is the Stabilizer Theorem. In the process, a systematic study of the structure of piecewise hyperdefinable sets is developed. In particular, we show the most significant properties of their logic topologies.

The Epistemology of Nondeterminism

This paper proposes new semantics for propositional dynamic logic (PDL), replacing the standard relational semantics. Under these new semantics, program execution is represented as fundamentally deterministic (i.e., functional), while nondeterminism emerges as an epistemic relationship between the agent and the system: intuitively, the nondeterministic outcomes of a given process are precisely those that cannot be ruled out in advance. We formalize these notions using topology and the framework of dynamic topological logic (DTL) (Kremer and Mints in Ann Pure Appl Logic 131:133–158, 2005). We show that DTL can be used to interpret the language of PDL in a manner that captures the intuition above, and moreover that continuous functions in this setting correspond exactly to deterministic processes. We also prove that certain axiomatizations of PDL remain sound and complete with respect to the corresponding classes of dynamic topological models. Finally, we extend the framework to incorporate knowledge using the machinery of subset space logic (Dabrowski et al. in Ann Pure Appl Logic 78:73–110, 1996), and show that the topological interpretation of public announcements as given in Bjorndahl (in: van Ditmarsch and Sandu (eds) Jaakko Hintikka on knowledge and game theoretical semantics, outstanding contributions to Logic, vol 12, Springer, 2018) coincides exactly with a natural interpretation of test programs.

Scan Chain Stitching based on Logic Topology for Test-Power Reduction under Routing Constraint

Scan architecture is a widely used design modification for testability in ASICs to obtain good test coverage. But during the process of scan testing, power consumption is much higher than in functional mode of operation, as all the flops in the design switch during scan shift operations (shift-in and shift-out). The heat generated from high power dissipation can destroy the chip, cause reliability problems, or induce noise. Sometimes the problem of wrong response due to overheating may arise, causing yield loss. For these reasons, test power reduction is a topic for research. Though there are several scan shift power optimization techniques used in practice, scan chain stitching techniques based on logic topology proposed in the recent years address both shift-in and shift-out powers. Conceptually, the techniques likely cause routing congestion and therefore applying the techniques under a routing constraint could be an optimal solution is the proposal presented in this paper.

Scan Chain Stitching based on Logic Topology for Test-Power Reduction under Routing Constraint

Scan Chain Stitching based on Logic Topology for Test-Power Reduction under Routing Constraint

Risk assessment of dammed lakes in China based on Bayesian network

Scientific risk assessment of dammed lakes is vitally important for emergency response planning. In this study, based on the evolution process of the disaster chain, the logic topology structure of dammed lake risk was developed. Then, a quantitative risk assessment model of dammed lake using Bayesian network is developed, which includes three modules of dammed lake hazard evaluation, outburst flood routing simulation, and loss assessment. In the model, the network nodes of each module were quantified using statistical data, empirical model, logical inference, and Monte Carlo method. The failure probability of a dammed lake, and the losses of life and property were calculated. This can be multiplied to assess the risk a dammed lake imposes after the uniformization of each loss type. Based on the socio-economic development and longevity statistics of dammed lakes, a risk-level classification method for dammed lakes is proposed. The Baige dammed lake, which emerged in China in 2018, was chosen as a case study and a risk assessment was conducted. The obtained results showed that the comprehensive risk index of Baige dammed lake is 0.7339 under the condition without manual intervention, identifying it as the extra-high level according to the classification. These results are in accordance with the actual condition, which corroborates the reasonability of the proposed model. The model can quickly and quantitatively evaluate the overall risk of a dammed lake and provide a reference for decision-making in a rapid emergency response scenario.

Research on topology adaptive method of distributed feeder automation based on IEC 61850

AbstractDistributed feeder automation (FA) needs to automatically recognize the changes in the feeder topology in real-time and has to configure the application topology of the corresponding distributed functions. This paper analyzes the application topology’s requirements when implementing distributed FA for the feeder equipped with a smart terminal unit (STU) and a fault passage indicator (FPI). Based on IEC 61850, the functional logic node and topology configuration of intelligent electronic devices (IEDs) are studied. The application topology identification and data flow dynamic binding methods for fault location, fault isolation, and power supply restoration are proposed. A case study verifies the effectiveness of the proposed method.

Topological Phononic Logic

Topological metamaterials have robust properties engineered from their macroscopic arrangement, rather than their microscopic constituency. They can be designed by starting from Dirac metamaterials with either symmetry-enforced or accidental degeneracy. The latter case provides greater flexibility in the design of topological switches, waveguides, and cloaking devices, because a large number of tuning parameters can be used to break the degeneracy and induce a topological phase. However, the design of a topological logic element-a switch that can be controlled by the output of a separate switch-remains elusive. Here we numerically demonstrate a topological logic gate for ultrasound by exploiting the large phase space of accidental degeneracies in a honeycomb lattice. We find that a degeneracy can be broken by six physical parameters, and we show how to tune these parameters to create a phononic switch that transitions between a topological waveguide and a trivial insulator by ultrasonic heating. Our design scheme is directly applicable to photonic crystals and may guide the design of future electronic topological transistors.

Using Ultrafilters to Prove Ramsey-type Theorems

Ultrafilters are a tool, originating in mathematical logic and general topology, that has steadily found more and more uses in multiple areas of mathematics, such as combinatorics, dynamics, and algebra, among others. The purpose of this article is to introduce ultrafilters in a friendly manner and present some applications to the branch of combinatorics known as Ramsey theory, culminating with a new ultrafilter-based proof of van der Waerden’s theorem.

Co-Design of Consensus-Based Approach and Reliable Communication Protocol for Vehicular Platoon Control

Automated and coordinated vehicle platoon driving is challenging as the complexity of vehicle control and the presence of unreliable wireless inter-vehicle communication. This subject has an interdisciplinary nature, involving control theories, vehicle dynamics, and communication. Due to the constant interaction between control logic and communication topology, a co-design approach for the controller and for reliable communication protocol becomes necessary. This paper describes the AddP-CACC - a consensus-based solution to vehicle platoons. The proposed solution turns the communication topology into a design parameter that dynamically reconfigures the controller. In addition, the controller automatically compensates for outdated information caused by network losses and delays. AddP-CACC was implemented in the PLEXE tool and was compared with other related works. Simulation results have shown the robustness and performance of the proposed solution in various scenarios that would include realistic propagation conditions with interference caused by other vehicles. The results have also evidenced the ability of the proposed solution to maintain a stable vehicular platoon by using different communication topologies, different vehicle flows, even in the presence of strong interferences, delays, and fading conditions.

Finding gene network topologies for given biological function with recurrent neural network

Searching for possible biochemical networks that perform a certain function is a challenge in systems biology. For simple functions and small networks, this can be achieved through an exhaustive search of the network topology space. However, it is difficult to scale this approach up to larger networks and more complex functions. Here we tackle this problem by training a recurrent neural network (RNN) to perform the desired function. By developing a systematic perturbative method to interrogate the successfully trained RNNs, we are able to distill the underlying regulatory network among the biological elements (genes, proteins, etc.). Furthermore, we show several cases where the regulation networks found by RNN can achieve the desired biological function when its edges are expressed by more realistic response functions, such as the Hill-function. This method can be used to link topology and function by helping uncover the regulation logic and network topology for complex tasks.

Pillay's conjecture for groups definable in weakly o‐minimal non‐valuational structures

Let G be a group definable in a weakly o-minimal non-valuational structure M. Then G / G 00 , equipped with the logic topology, is a compact Lie group, and if G has finitely satisfiable generics, then dim ( G / G 00 ) = dim ( G ) . Our main technical result is that G is a dense subgroup of a group definable in the canonical o-minimal extension of M.

Distribution Network Topology Identification Based on IEC 61850 Logical Nodes

Distributed control has good real-time performance and can better meet the control requirements of active distribution networks with a large number of distributed generations. Some distributed applications require real-time feeder topology to achieve control. In this paper, the demand for distributed control applications for feeder real-time topology is analyzed. Based on IEC 61850 modeling method, a new cell topology logic node and a new topology slice node are built to express feeder topology. Using the topology information of smart terminal unit (STU) configuration and the current status information of switchgear, based on the depth-first search, the feeder real-time topology identification can be realized, which meets the application requirements of distributed control. The study case verified the effectiveness of the method.

Low‐voltage and high‐speed stand‐alone multiple‐input complex gates for error correction coding applications

SummaryThis paper presents two low‐voltage high‐speed shallow‐depth current mode logic (CML) topologies. The number of stacked transistors of these proposed structures decreases between VDD to GND. Reduce stacks in proposed gates enhance the circuit to operate at lower supply voltages. Therefore, the proposed logic causes to use of a stand‐alone multiple‐input gate instead of a low‐input gate. The use of decomposing multiple‐input gate for some input series causes error in the output of the circuit. In advanced technologies with size scaling down, the reliability and correctness of data in memories are essential issues. Error correction codes (ECCs) are used for protecting memories against faults. Reducing power consumption with preserving speed is vital in the design of ECCs. The units of ECCs are composed of multiple‐input gates; hence, using a low‐voltage high‐performance structure is required. The essential properties of the proposed logic are low‐voltage and high‐speed operation modes. It also gains in delay improvement of the proposed structure and multiple‐tailed current mode logic (MTCML) than source‐coupled logic (SCL) about 27% and 21% in the low‐voltage design. The final power delay product (PDP) of proposed logic and MTCML is improved by about 14% and 11% than SCL.