Top-gate Thin-film Transistors Research Articles

A Practical Model Assessing the Degradation of Polycrystalline Silicon TFTs Due to DC Electrical Stress

Degradation phenomena under the application of a variety of hot-carrier stress conditions were investigated in n-channel top-gate polysilicon thin-film transistors of various channel widths, fabricated by sequential lateral solidification excimer laser annealing. A simple and practical model was developed in order to predict the dc-stress-induced degradation and the evolution during stress of the critical electrical parameters of device performance, such as the threshold voltage. The presented model suggests a series combination of a defective and a nondefective region of the device's channel. It was found that the spreading of the damaged region along the channel from the drain toward the source is width dependent. In order to investigate that, devices with different channel widths were compared. By extracting and monitoring the electrical parameters in the linear regime of operation, after each stress cycle, the fitted results of the model were compared and evaluated.

Performance of top-gate thin film transistors with solution processed ZnO channel layer and PVP gate dielectric

The performance of top-gate thin film transistors with solution processed zinc oxide (ZnO) channel layer and poly(4-vinylphenol) (PVP) gate dielectric have been investigated. The transparency of the PVP film was more than 80% in the visible region, indicating that PVP can be used as a potential dielectric layer for transparent electronics. The TFTs with as-prepared ZnO as the channel layer showed a saturation field effect mobility of 6.4 × 10−3 cm2/Vs with an on/off ratio of 30. The performances of the TFTs were enhanced after oxygen annealing of the ZnO channel layer prior to PVP deposition. The TFTs with 1 h oxygen annealed ZnO as the channel layer showed a saturation mobility of 0.05 cm2/Vs with an on/off ratio of 2.1 × 102. The obtained results are encouraging for fabrication of all solution processed ZnO based TFTs for cost effective technological applications.

Low‐Voltage Ring Oscillators Based on Polyelectrolyte‐Gated Polymer Thin‐Film Transistors

A polyanionic electrolyte is used as gate insulator in top-gate p-channel polymer thin-film transistors. The high capacitance of the polyelectrolyte film allows the transistors and integrated circuits to operate below 1.5 V. Seven-stage ring oscillators that operate at supply voltages down to 0.9 V and exhibit signal propagation delays as low as 300 µs per stage are reported.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Impact of device configuration on the temperature instability of Al–Zn–Sn–O thin film transistors

We compared the effect of the temperature on the device stability of Al–Zn–Sn–O (AZTO) thin film transistors (TFTs) with top gate and bottom gate architectures. While the bottom gate device without any passivation layer on the AZTO channel layer showed a large threshold voltage (Vth) shift of 1.6 V after heating it from 298 to 398 K, the naturally passivated top gate device exhibited a smaller Vth shift of 0.6 V. This different behavior is discussed based on the concept of the thermal activation energy of the subthreshold drain current. It is proposed that the suitable passivation and lower interfacial trap density for the top gate TFT are responsible for its superior temperature stability compared to the bottom gate device.

Transparent dual-gate InGaZnO thin film transistors: OR gate operation

Transparent dual-gate (DG) InGaZnO4 thin film transistors for OR logic operation were fabricated on a glass substrate. A 100-nm-thick SiO2 layer used as both top and bottom gate dielectrics was deposited by plasma enhance chemical vapor deposition at 200°C. Compared to bottom gate, top gate thin film transistors (TFTs) exhibited better device performance with higher saturation mobility, drain current on-to-off ratio, lower threshold voltage, and subthreshold gate-voltage swing. This improved performance was mainly attributed to low process-induced damage or low parasitic capacitance between gate and source/drain and low parasitic resistance between channel and source/drain in top-contact TFT configuration (coplanar type). DG-mode TFTs showed saturation mobility of ∼16.9cm2V−1s−1, drain current on-to-off ratio of ∼1×106, subthreshold gate-voltage swing of ∼0.33Vdecade−1, and threshold voltage of ∼1.25V. The results demonstrate that DG InGaZnO4 TFTs are effective in improving the device performance because the channel layer is modulated independently by a top or, bottom gate signal and are well suited for OR gate operation.

Instability Behavior of Oxide-based Top-gate TFTs under Electrical and Optical Stress Test

We report instability behavior of oxide-based top-gate thin-film transistors under electrical and optical stresses. For electrical stress, transfer curve shifts to the right and left for positive and negative gate stress voltages, respectively, while sub-threshold slope (SS) barely changed for both cases. Although this behavior is consistent with the previously reported oxide-based TFT instability behavior explained by charge trapping mechanism, threshold voltage shift seemed to have power-law-time dependency unlike the previous results. We also tested optical stress behavior of the oxide-based TFTs with a blue power-LED. Under prolonged exposure of 3.5mW/cm2 blue light, both transfer curves under dark and illumination conditions shift to the left, but with significant change in sub-threshold slope for illumination condition. After the electrical and optical stress tests, stress effect was relaxed without any annealing process.

P -channel thin-film transistor using p-type oxide semiconductor, SnO

This paper reports that among known p-type oxide semiconductors, tin monoxide (SnO) has a high hole mobility and produces good p-type oxide thin-film transistors (TFTs). Device-quality SnO films were grown epitaxially on (001) yttria-stabilized zirconia substrates at 575°C by pulsed laser deposition. These exhibited a Hall mobility of 2.4cm2V−1s−1 at room temperature. Top-gated TFTs, using epitaxial SnO channels, exhibited field-effect mobilities of 1.3cm2V−1s−1, on/off current ratios of ∼102, and threshold voltages of 4.8V.

Top-Gate Amorphous Silicon TFT With Self-Aligned Silicide Source/Drain and High Mobility

We report a process for top-gate amorphous silicon thin-film transistors (alpha-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280degC. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ~2.7 V, saturation electron field-effect mobility of 1.0 cm2/V ldr s, subthreshold slope of 600 mV/dec, and on/off ratio of ~2 times 106. These top-gate alpha-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate alpha-Si TFTs. Our results suggest that the top-gate alpha-Si TFT geometry merits reevaluation for industrial use.

Improved dynamic properties of ZnO-based photo-transistor with polymer gate dielectric by ultraviolet treatment

The authors report on the fabrication of photo-detecting top-gate ZnO-based thin-film transistors (ZnO-TFTs) with poly-4-vinylphenol (PVP) polymer gate dielectric. A ZnO channel surface was treated by intense ultraviolet (UV, wavelength of 352 nm) before making contacts with PVP dielectric. Although our UV-treated devices showed lower on-state current than untreated pristine ones, the former also displayed orders of magnitude lower off-state current than the latter. We applied the UV-treated devices for enhancing their photo-detection properties, which basically needs low off-state current. Under a modulated photon signal (10 Hz, 364 nm) for the UV detection measurements, our photo-inverter with UV-treated ZnO-TFT exhibited a good dynamic property of ∼30 ms operating at 5 V.

Top-gate ZnO thin-film transistors with a polymer dielectric designed for ultraviolet optical gating

We report on the fabrication of ultraviolet (UV)-sensing top-gate ZnO thin-film transistors (TFTs) with a poly-4-vinylphenol (PVP) polymer gate dielectric on glass substrate. Our top-gate ZnO-TFT showed a field-effect mobility of 0.05 cm 2/V s, maximum saturation current of 0.11 μA at a gate bias of 10 V and an on/off ratio of ∼10 3 in the dark. Under UV illumination with a wavelength of 364 nm the ZnO-TFT exhibited ∼4.7 μA for a drain current (at the same gate bias of 10 V), which is ∼50 times higher than without UV. Such photo-transistor action appeared more pronounced under a depletion regime of 0 V gate bias and the photo-to-dark current ratio was more than about 10 4. By adopting this high UV-sensitivity, our inverter device with the top-gate ZnO-TFT and a load resistance well demonstrated its optical gating behavior.

Electrically stable low voltage ZnO transistors with organic/inorganic nanohybrid dielectrics

We report on the fabrication of top-gate ZnO thin-film transistors (TFTs) with organic and inorganic nanohybrid dielectric layers that take superlattice form in their inside structure. The nanohybrid dielectrics were prepared by the alternate deposition of organic self-assembled monolayer and oxide monolayer on sputter-deposited ZnO channel. With a 22-nm-thin AlOx-based hybrid dielectric layer (∼130nFcm2), our ZnO TFT showed a field mobility of 0.36cm2Vs operating at 8V, while the mobility increased up to 0.66cm2Vs with a 22-nm-thin AlOx-based/TiOx-based/AlOx-based (5.5nm11nm5.5nm and ∼220nFcm2) triple hybrid layer under 2V operation. Since both ZnO-TFTs display little gate hysteresis, we conclude that our nanohybrid dielectric approach is promising to achieve a gate-stable low voltage top-gate ZnO-TFTs.

Polycrystalline silicon thin-film transistors on quartz fiber

We demonstrate the fabrication of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) on a thin quartz fiber for the first time. The poly-Si used in the active layer of the TFTs was prepared by excimer laser annealing of an amorphous Si thin film deposited on the fiber. Top-gated TFTs were fabricated on the fiber, and a field effect mobility of 10cm2∕Vs was obtained. The proposed TFTs on a thin quartz fiber, named fiber TFTs, have potential application in microelectronic devices using TFTs fabricated on one-dimensional substrates.

ZnO-based nonvolatile memory thin-film transistors with polymer dielectric/ferroelectric double gate insulators

The authors report on the fabrication of a top-gate ZnO thin-film transistor (TFT) with a polymer dielectric/ferroelectric double-layer gate insulator that was formed on patterned ZnO through a sequential spin-casting process of 450-nm-thick poly-4-vinylphenol (PVP) and 200-nm-thick poly(vinylidene fluoride/trifluoroethylene) [P(VDF/TrFE)]. Compared to the single P(VDF/TrFE) layer, double layer shows remarkably reduced leakage current with the aid of the PVP buffer. TFT with the PVP/P(VDF/TrFE) double layer exhibits a field effect mobility of 0.36cm2∕V and a large memory hysteresis in the transfer characteristics due to the ferroelectric P(VDF/TrFE). The retention of the device lasted over 2h.

Amorphous oxide channel TFTs

Thin film transistors (TFTs) using amorphous oxides of post-transition metals: indium, gallium, and zinc for the channel materials are fabricated with radio-frequency magnetron sputtering methods for the deposition of the channel and the gate insulator layers, at room temperature with no high-temperature post-deposition annealing process. The TFTs operate as n-channel field-effect transistors with various structures of top/bottom gate and top/bottom source-and-drain contact including the inverse-stagger types, and with various materials for the gate insulators, the electrodes, and the substrates. The TFTs having smoother channel interfaces show the better performance at the saturation mobility beyond 10 cm2 V−1 s−1 and the on-to-off current ratio over 108 than the rough channel interfaces. The ring oscillator circuits operate with five-stage inverters of the top-gate TFTs or the inverse-stagger TFTs. Organic light-emission diode cells are driven by a simple circuit of the TFTs. It is also found by a combinatorial approach to the material exploration that the TFT characteristics can be controlled by the composition ratio of the metals in the channel layers. The amorphous oxide channel TFTs fabricated with sputtering deposition at low temperature could be a candidate for key devices of large-area flexible electronics.

Fabrication of thin-film transistors based on CdTe/CdHgTe core-shell nanocrystals

Electrical characteristics of field-effect thin-film transistors (TFTs) with p-channels composed of CdTe/CdHgTe core-shell nanocrystals are investigated in this work. For the fabrication of bottom- and top-gate TFTs, CdTe/CdHgTe core-shell nanocrystals synthesized by the colloidal method are first dispersed on oxidized p + Si substrates by spin-coating, the dispersed nanocrystals are sintered at 150 °C to form the channels for the TFTs, and Al 2O 3 layers are deposited on the channels. A representative bottom-gate field-effect TFT with a bottom-gate SiO 2 layer exhibits a mobility of 0.21 cm 2/V s and an I on/ I off ratio of 1.5 × 10 2, and a representative top-gate field-effect TFT with a top-gate Al 2O 3 layer provides a field-effect mobility of 0.026 cm 2/V s and an I on/ I off ratio of 2.5 × 10 2. The CdTe/CdHgTe nanocrystal-based TFTs with bottom- and top-gate geometries are compared in this paper.

Transparent ZnO thin film transistor fabricated by sol-gel and chemical bath deposition combination method

Top-gate thin film transistors with n-type ZnO active channel were performed under 230°C. Especially, ZnO film was deposited by a combined method of sol-gel and chemical bath deposition without any preactivation for film growth. Silicon nitride and indium tin oxide were used as the gate insulator and the conducting electrodes (source, drain, and gate). These transistors were highly transparent in the visible spectrum, with transmittance as high as 75% to approximately 85% at wavelength from 500to700nm. The optimum device has field-effect mobility of 0.67cm2∕Vs and an on-off ratio more than 107.

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiNx) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.

Bottom- and top-gate field-effect thin-film transistors with p channels of sintered HgTe nanocrystals

Sintered HgTe nanocrystal-based thin-film transistors (TFTs) with bottom- and top-gate geometries were fabricated at a temperature of 150°C by spin coating in this work. The SiO2 bottom- and Al2O3 top-gate field-effect TFTs with p channels composed of sintered HgTe nanocrystals exhibit high carrier mobilities of 0.82 and 2.38cm2∕Vs, respectively. The operating gate voltages for the top-gate transistor with an Al2O3 dielectric layer are actually lower, compared with the SiO2 bottom-gate transistor. The electrical characteristics of these TFTs are discussed in more detail in this letter.

Low-voltage-driven top-gate ZnO thin-film transistors with polymer/high-k oxide double-layer dielectric

The authors report on the fabrication of a low-voltage-driven top-gate ZnO thin-film transistor with a polymer/high-k oxide double-layer dielectric. Hybrid double-layer dielectric (k=∼9.8) was formed on patterned ZnO through sequential deposition processes: spin casting of 45-nm-thin poly-4-vinylphenol and e-beam evaporation of 50-nm-thick amorphous high-k oxide (CeO2–SiO2 mixture). Room-temperature-deposited ZnO channel exhibits much rougher surfaces compared to that of 100°C deposited ZnO, so that enhanced device performances were achieved from a ZnO thin-film transistor (TFT) prepared with 100°C deposited ZnO: ∼0.48cm2∕Vs for field-effect mobility and ∼5×103 for on/off current ratio. Adopting our top-gate ZnO-TFT, a load-resistance inverter was set up and demonstrated decent static and dynamic operations at 3V.