Top-gated Graphene Transistors Research Articles

Investigating the Device Performance Variation of a Buried Locally Gated Al/Al2O3 Graphene Field-Effect Transistor Process

In this study, a process is developed for the fabrication of buried top-gated graphene transistors with Al2O3 as a gate dielectric, yielding devices that can be suitable for not only flexible electronics but also laser-induced graphene (LIG)-based technology implementations. A new processing option is presented with the use of tetraethyl-orthosilicate (TEOS) as an etch stop for contact via etching of Al2O3. Buried locally gated Al/Al2O3 graphene field-effect transistors (GFETs) are fabricated with Dirac points as low as 4 V, with a metal-to-graphene contact resistance as low as ∼1.7 kΩ·µm, and an average hole mobility of 457.97 cm2/V·s with a non-uniformity of 93%. Large device variation and non-uniformity in electrical performance are not uncommon for graphene-based devices, as process-induced defects play a major role in such variation. AFM, SEM, Raman spectroscopy, and model fitting indicated that the rough Al/Al2O3 surface was the main factor for the observed device variation. AFM analysis indicated a graphene surface roughness Ra of 16.19 nm on top of the buried Al/Al2O3 gate in contrast to a Ra of 4.06 nm over Al2O3/SiO2. The results presented indicate the need to reduce device variability and non-uniformity by improving transfer methods, as well as the use of smoother surfaces and compatible materials. The presented analyses provide a framework with which other researchers can analyze and correlate device variation and non-uniformities while methods to reduce variability are investigated.

2D Electronics Based on Graphene Field Effect Transistors: Tutorial for Modelling and Simulation.

This paper provides modeling and simulation insights into field-effect transistors based on graphene (GFET), focusing on the devices’ architecture with regards to the position of the gate (top-gated graphene transistors, back-gated graphene transistors, and top-/back-gated graphene transistors), substrate (silicon, silicon carbide, and quartz/glass), and the graphene growth (CVD, CVD on SiC, and mechanical exfoliation). These aspects are explored and discussed in order to facilitate the selection of the appropriate topology for system-level design, based on the most common topologies. Since most of the GFET models reported in the literature are complex and hard to understand, a model of a GFET was implemented and made available in MATLAB, Verilog in Cadence, and VHDL-AMS in Simplorer—useful tools for circuit designers with different backgrounds. A tutorial is presented, enabling the researchers to easily implement the model to predict the performance of their devices. In short, this paper aims to provide the initial knowledge and tools for researchers willing to use GFETs in their designs at the system level, who are looking to implement an initial setup that allows the inclusion of the performance of GFETs.

N-Doped Graphene with Low Intrinsic Defect Densities via a Solid Source Doping Technique

N-doped graphene with low intrinsic defect densities was obtained by combining a solid source doping technique and chemical vapor deposition (CVD). The solid source for N-doping was embedded into the copper substrate by NH3 plasma immersion. During the treatment, NH3 plasma radicals not only flattened the Cu substrate such that the root-mean-square roughness value gradually decreased from 51.9 nm to 15.5 nm but also enhanced the nitrogen content in the Cu substrate. The smooth surface of copper enables good control of graphene growth and the decoupling of height fluctuations and ripple effects, which compensate for the Coulomb scattering by nitrogen incorporation. On the other hand, the nitrogen atoms on the pre-treated Cu surface enable nitrogen incorporation with low defect densities, causing less damage to the graphene structure during the process. Most incorporated nitrogen atoms are found in the pyrrolic configuration, with the nitrogen fraction ranging from 1.64% to 3.05%, while the samples exhibit low defect densities, as revealed by Raman spectroscopy. In the top-gated graphene transistor measurement, N-doped graphene exhibits n-type behavior, and the obtained carrier mobilities are greater than 1100 cm2·V−1·s−1. In this study, an efficient and minimally damaging n-doping approach was proposed for graphene nanoelectronic applications.

Reprint of: Improvements on thermal stability of graphene and top gate graphene transistors by Ar annealing

Thermal annealing of graphene was studied to improve the thermal stability. During the annealing under an Ar atmosphere with temperature from 100 °C to 600 °C, graphene exhibits partial removal of PMMA residues, low density of defect cracks in SEM images and relatively low ID/IG ratios in Raman spectrum probing. For a top-gated graphene transistor with thermal annealing, it performs high carrier mobility up to 3500 cm2 V−1 s−1 and slightly asymmetric bipolar behaviours as well as slight Dirac point variation within ±0.2 V.

A triboelectric charge top-gated graphene transistor

A graphene channel with polymer polymethyl methacrylate (PMMA) or Polydimethylsiloxane (PDMS) passive layer were fabricated on a Si/SiO2 substrate. The gate-effect of triboelectric charges on a foreign stimulator and in situ generated triboelectric charges on the passive layer are tested by controlling the foreign stimulator (PDMS or Acrylic plate) touch or not with the passive layer. When the negatively charged PDMS (positively charged Acrylic) stimulator approach and leave the device without touching the passive layer, the channel resistance shows a pulsed decrease (increase) with amplitude less than 1%. When the stimulator has a temporary touch with the passive layer, the in situ generated triboelectric charges on the PMMA (PDMS) passive layer cause stepwise increase (decrease) of the channel resistance. The amplitude of the resistance change steps of the device with PMMA passive layer (2μm in thickness) is about one order larger for than that of the device with PDMS passive layer (about 60μm in thickness). The significant different response of the device depending on whether the stimulator touches or not with the passive layer suggests two possible operation models for the tribo-charge top-gated graphene channel. It may enable diverse design of tactile sensors and pressure sensors based on the tribotronic effect.

Improvements on thermal stability of graphene and top gate graphene transistors by Ar annealing

Thermal annealing of graphene was studied to improve the thermal stability. During the annealing under an Ar atmosphere with temperature from 100 °C to 600 °C, graphene exhibits partial removal of PMMA residues, low density of defect cracks in SEM images and relatively low ID/IG ratios in Raman spectrum probing. For a top-gated graphene transistor with thermal annealing, it performs high carrier mobility up to 3500 cm2 V−1 s−1 and slightly asymmetric bipolar behaviours as well as slight Dirac point variation within ±0.2 V.

Electrical Characteristics of Top-Gated Graphene Field Effect Transistors Fabricated on Stainless Steel (STS) Substrate.

Top-gated Graphene transistors with Al2O3 gate-dielectric on the flexible stainless steel substrate have been demonstrated. Graphene was synthesized on copper foil using a chemical vapor deposition method and transferred onto the stainless steel substrate by wet transfer technique. The stainless steel substrate was polished by chemical mechanical polishing method and the spin-on-glass layer was coated on the surface to improve the surface roughness. The average surface roughness R(a) was as low as 5.9 nm from the AFM measurement. The measured hole and electron mobilities from the current-voltage characteristics at room temperature were calculated as high as 310 and 45 cm2/Vs, respectively. In addition, the effect of surrounding temperature up to 355 K on the electrical variations was investigated. The mobility was inversely proportional to the temperature with negligible hysteresis where the temperature coefficient was calculated as low as -0.65 %/K.

Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors

We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-k dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 us, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple DC characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/um. In addition, using modeling and capacitance-voltage measurements we extract charge trap densities up to 10^12 1/cm^2 in the top gate dielectric (here Al2O3). Our study illustrates important time- and field-dependent imperfections of top-gated GFETs with high-k dielectrics, which must be carefully considered for future developments of this technology

Reducing Contact Resistance in Graphene Devices through Contact Area Patterning

Performance of graphene electronics is limited by contact resistance associated with the metal-graphene (M-G) interface, where unique transport challenges arise as carriers are injected from a 3D metal into a 2D-graphene sheet. In this work, enhanced carrier injection is experimentally achieved in graphene devices by forming cuts in the graphene within the contact regions. These cuts are oriented normal to the channel and facilitate bonding between the contact metal and carbon atoms at the graphene cut edges, reproducibly maximizing "edge-contacted" injection. Despite the reduction in M-G contact area caused by these cuts, we find that a 32% reduction in contact resistance results in Cu-contacted, two-terminal devices, while a 22% reduction is achieved for top-gated graphene transistors with Pd contacts as compared to conventionally fabricated devices. The crucial role of contact annealing to facilitate this improvement is also elucidated. This simple approach provides a reliable and reproducible means of lowering contact resistance in graphene devices to bolster performance. Importantly, this enhancement requires no additional processing steps.

Dual top gated graphene transistor in the quantum Hall regime

We study the effect of local modulation of charge density and carrier type in graphene field effect transistors using a double top gate geometry. The two top gates lead to the formation of multiple p–n junctions. Electron transport measurements at low temperature and in the presence of magnetic field show various integer and fractionally quantized conductance plateaus. We explain these results based on the mixing of the edge channels and find that inhomogeneity plays an important role in defining the exact quantization of these plateaus, an issue critical for applications of p–n junctions.

Graphene Ambipolar Multiplier Phase Detector

We report the experimental demonstration of a multiplier phase detector implemented with a single top-gated graphene transistor. Ambipolar current conduction in graphene transistors enables simplification of the design of the multiplier phase detector and reduces its complexity in comparison to phase detectors based on conventional unipolar transistors. Fabrication of top-gated graphene transistors is essential to achieve the higher gain necessary to demonstrate phase detection. We report a phase detector gain of -7 mV/rad in this letter. An analysis of key technological parameters of the graphene transistor, including series resistance, top-gate insulator thickness, and output resistance, indicates that the phase detector gain can be improved by as much as two orders of magnitude.

The role of charge traps in inducing hysteresis: Capacitance–voltage measurements on top gated bilayer graphene

Understanding the origin of hysteresis in the channel resistance from top gated graphene transistors is important for transistor applications. Capacitance - voltage measurements across the gate oxide on top gated bilayer graphene show hysteresis with a charging and discharging time constant of ~100 {\mu}s. However, the measured capacitance across the graphene channel does not show any hysteresis, but shows an abrupt jump at a high channel voltage due to the emergence of an order, indicating that the origin of hysteresis between gate and source is due to charge traps present in the gate oxide and graphene interface.

Impact of Graphene Interface Quality on Contact Resistance and RF Device Performance

This letter demonstrates the importance of the graphene/metal interface on the ohmic contacts of high-frequency graphene transistors grown by chemical vapor deposition (CVD) on copper. Using an Al sacrificial layer during ohmic lithography, the graphene surface roughness underneath the ohmic contacts is reduced by fourfold, resulting in an improvement in the contact resistance from 2.0 to 0.2-0.5 kΩ·μm. Using this technology, top-gated CVD graphene transistors achieved direct-current transconductances of 200 mS/mm, maximum on current densities in excess of 1000 mA/mm, and hole mobilities ~ 1500-3000 cm2/(V·s) on silicon substrates. Radio-frequency device performance yielded an extrinsic current-gain cutoff frequency fT of 12 GHz after pad capacitance de-embedding resulting in an fT - LG product of 24 GHz·μm.

Top-Gated Chemical Vapor Deposition Grown Graphene Transistors with Current Saturation

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Approaching Terahertz Graphene Transistors

Graphene is emerging as an attractive electronic material for future electronics due to its exceptionally high carrier mobility and single-atomic thickness. However, the conventional dielectric integration and device fabrication processes cannot be readily applied to graphene transistors because they can often introduce substantial defects into the monolayer of carbon lattices and severely degrade the device performance. Here we describe a new strategy to fabricate high performance graphene transistors through the hetero-integration of graphene with inorganic nanostructures. First, I will describe the fabrication of high mobility top-gated graphene transistors by first synthesizing free-standing high-k oxide nanostructures and then transferring them onto graphene as top-gate dielectrics. We show that single crystalline Al2O3 nanoribbons can be synthesized with excellent dielectric properties, and can be used as the top-gate dielectrics to enable graphene transistors with the highest carrier mobility exceeding 20,000 cm2/V•s. Furthermore, we describe a self-aligned approach using a metal-dielectric core-shell nanowire as the top-gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. This fabrication approach preserves the high carrier mobility in graphene, and ensures nearly perfect alignment between source, drain, and gate electrodes. It therefore affords unprecedented transistor performance with the projected intrinsic cut-off frequency approaching terahertz regime.

Scalable templated growth of graphene nanoribbons on SiC

In spite of its excellent electronic properties, the use of graphene in field-effect transistors is not practical at room temperature without modification of its intrinsically semimetallic nature to introduce a bandgap. Quantum confinement effects can create a bandgap in graphene nanoribbons, but existing nanoribbon fabrication methods are slow and often produce disordered edges that compromise electronic properties. Here, we demonstrate the self-organized growth of graphene nanoribbons on a templated silicon carbide substrate prepared using scalable photolithography and microelectronics processing. Direct nanoribbon growth avoids the need for damaging post-processing. Raman spectroscopy, high-resolution transmission electron microscopy and electrostatic force microscopy confirm that nanoribbons as narrow as 40 nm can be grown at specified positions on the substrate. Our prototype graphene devices exhibit quantum confinement at low temperatures (4 K), and an on-off ratio of 10 and carrier mobilities up to 2,700 cm(2) V(-1) s(-1) at room temperature. We demonstrate the scalability of this approach by fabricating 10,000 top-gated graphene transistors on a 0.24-cm(2) SiC chip, which is the largest density of graphene devices reported to date.

High- κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

Deposition of high-kappa dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-kappa dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-kappa dielectrics with graphene by first synthesizing freestanding high-kappa oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al(2)O(3) nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm(2)/V x s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-kappa dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics.

Top gated graphene transistors with different gate insulators

AbstractTop gated graphene field effect transistors with AlN and Si3N4 gate insulator materials were fabricated by plasma assisted deposition. Transistors with an AlN top gate insulator showed a reduced mobility and channel carrier density, whereas for the transistors with Si3N4 dielectric an increase of the mobility and a decrease of the channel carrier density was observed. The reduced carrier density can be explained by bond formation between the insulator and the graphene sheets. The different behaviour of the carrier mobility is due to defect passivation by H2 in case of Si3N4 and defect formation in the graphene channel for the AlN gate insulator. A reduced transconductance in top gate device configurations compared to the back gate configurations was observed, which can be caused by the Klein paradox or differences in the trap densities in the top gate insulators. (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Utilization of a Buffered Dielectric to Achieve High Field-Effect Carrier Mobility in Graphene Transistors

We utilize an organic polymer buffer layer between graphene and conventional gate dielectrics in top-gated graphene transistors. Unlike other insulators, this dielectric stack does not significantly degrade carrier mobility, allowing for high field-effect mobilities to be retained in top-gate operation. This is demonstrated in both two-point and four-point analysis and in the high-frequency operation of a graphene transistor. Temperature dependence of the carrier mobility suggests that phonons are the dominant scatterers in these devices.

Operation of Graphene Transistors at Gigahertz Frequencies

Top-gated graphene transistors operating at high frequencies (gigahertz) have been fabricated and their characteristics analyzed. The measured intrinsic current gain shows an ideal 1/f frequency dependence, indicating a FET-like behavior for graphene transistors. The cutoff frequency f(T) is found to be proportional to the dc transconductance g(m) of the device, consistent with the relation f(T) = g(m)/(2piC(G)). The peak f(T) increases with a reduced gate length, and f(T) as high as 26 GHz is measured for a graphene transistor with a gate length of 150 nm. The work represents a significant step toward the realization of graphene-based electronics for high-frequency applications.