Top-gate Oxide Research Articles

9‐3: The Latest Technology Breakthroughs for 31” 4K Flexible Printed OLED TV Display Technology

The flexible printed OLED TV display technology will be able to create new application market, such as rollable/foldable TV, in the future. It's TV Mobiles. Since the TCL (TCL CSOT, Guangdong Juhua Printed Display Technology Co. Ltd. & TCL Corporate Research) has successfully demonstrated the 31” FHD flexible printed OLED TV, there are a lot of technology breakthroughs for improving the panel performance and cost reduction. The co‐planar top gate Oxide TFT device architecture, printing OLED top emission device architecture with new OLED materials, MURA free ink jet printing technology with unique bank design, advanced encapsulation technology with new inorganic material for panel performance improvement are developed. Especially innovative mechanical release technology without using laser lift off technology is developed for cost reduction and production yield up in flexible printed OLED TV MP line. Based on these technology breakthroughs, 31” 4K flexible printed OLED TV with high resolution(142ppi) are fabricated.The performance of 31” flexible printed OLED TV is, 4K high resolution (3840x2160, 142ppi), luminance: FW 150nits, excellent C/R; > 1M:1, color gamut: DCI‐P3: >99%, wide viewing angle (Δu'v' < 0.02): ≥ +/‐ 45°, A/R: 47.75%, and curvature radius: 20mmIn this paper, the panel performance of 31” 4K high resolution flexible printed OLED TV and the latest technology breakthroughs are discussed in details.

Process implications on the stability and reliability of 300 mm FAB MoS2 field-effect transistors

Recent advances in fabricating field-effect transistors with MoS2 and other related two-dimensional (2D) semiconductors have inspired the industry to begin with the integration of these emerging technologies into FAB-compatible process flows. Just like in the lab research on 2D devices performed in the last decade, focus during development is typically put on pure technology-related issues, such as low-temperature growth methods of large-area 2D films on target substrates, damage-free transfer from sacrificial substrates and growth of top-gate oxides. With maturing technology, the problem of stability limitations caused by oxide traps is gradually coming into focus now. Thus, here we report an in-depth analysis of hysteresis and bias-temperature instabilities for MoS2 FETs fabricated using a 300 mm FAB-compatible process. By performing a comprehensive statistical analysis on devices with top gate lengths ranging between 18 nm and 10 μm, we demonstrate that aggressive scaling results in additional stability problems, likely caused by defective edges of the scaled top gates, in particular at higher operation temperatures. These are important insights for understanding and addressing the stability limitations in future nanoscale 2D FETs produced using FAB process lines.

Investigating The Performance and Viability of Semiconducting Graphene as A Substitute for Silicon in Field Effect Transistors

This paper investigates the electrical and thermal properties of two competing methods of semiconducting graphene, doped graphene and reduced graphene oxide, and their respective viabilities for implementation in field effect transistors. We used the Graphene Field Effect Transistor (GFET) simulation software on nanohub.com to determine the current, voltage, and max temperature based on variations in the channel length, top gate oxide thickness, electron mobility, and thermal conductivity and then compared these performance results with those of a traditional silicon-based transistor. Our results demonstrated that doped graphene had superior current conductivity, higher electron mobility, higher thermal conductivity, and higher maximum temperature to those of reduced graphene oxide and silicon. Practicality wise, reduced graphene oxide is far easier to mass produce, as was found to still perform better than silicon-based transistors. Transistors form the backbone of the electronics industry; this study proves that a shift toward graphene-based transistors, doped ones especially, would make transistors stronger, more durable, and more efficient. With the already ubiquitous usage of transistors in our everyday lives, a switch to graphene could bring revolutionary benefits for electronics such as smarter cell phones, faster computers, and more accurate biosensors.

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

Engineering a Subnanometer Interface Tailoring Layer for Precise Hydrogen Incorporation and Defect Passivation for High-End Oxide Thin-Film Transistors.

Top-gate self-aligned structured oxide thin-film transistors (TFTs) are suitable for the backplanes of high-end displays because of their low parasitic capacitances. The gate insulator (GI) deposition process should be carefully designed to manufacture a highly stable, high-mobility oxide TFT, particularly for a top-gate structure. In this study, a nanometer-thick Al2O3 layer via plasma-enhanced atomic layer deposition (PE-ALD) is deposited on the top-gate bottom-contact structured oxide TFT as the interface tailoring layer, which can also act as the hydrogen barrier to modulate carrier generation from hydrogen incorporation into the active layer of the TFT during the following process such as postannealing. Al-doped InSnZnO (Al/ITZO) with an Al/In/Sn/Zn atomic ratio composition of 1.7:24.3:40:34 was used for high mobility oxide semiconductors, and an Al2O3/Si3N4 bilayer was used for the GI. The degradation issue due to the excellent barrier characteristics of Al2O3 and Si3N4 can be minimized. An oxide TFT fabricated without the interface tailoring layer exhibits conductor-like characteristics owing to the excessive carrier generation by hydrogen incorporation. However, TFTs with additional interface layers exhibit reasonable characteristics and distinct trends in electrical characteristics depending on the thicknesses of the interface layers. The optimized devices exhibit an average turn-on voltage (Von) of -0.31 V with 33.63 cm2/(V s) of high mobility and 0.09 V/dec of subthreshold swing value. The interfaces between the active layer and hydrogen barriers were investigated using a high-resolution transmission electron microscope, contact angle measurement, and secondary ion mass spectroscopy to reveal the origin of the trends in properties between the devices. The top-gate device with a hydrogen barrier using the four-cycle deposition exhibits optimum electrical characteristics of both high mobility and good stability with only a 0.04 V shift of Von under positive-bias temperature stress (PBTS). We realize a high-end, self-aligned TFT with high mobility [34.7 cm2/(V s)] and negligible Von shift of -0.06 V under PBTS by applying a subnanometer hydrogen barrier.

High-Performance Short-Channel Top-Gate Indium-Tin-Oxide Transistors by Optimized Gate Dielectric

In this work, high-performance top-gate indium-tin-oxide (ITO) transistors with high carrier mobility of 60 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V∙s have been successfully demonstrated using optimized atomic layer deposited (ALD) La-doped HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as the top-gate dielectric. The scaled device with a channel length of 50 nm exhibits a high current on/off ratio over 7×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> owing to the excellent electrostatic control. A maximum output current of 1680 μA/μm with a remarkable carrier velocity of 0.87×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cm/s has also been achieved due to the record low contact resistance of 180 Ω∙μm. The on- and off-state performance of our ITO transistors are the highest among previous top-gate amorphous oxide semiconductors.

Ultra-thin gate insulator of atomic-layer-deposited AlO x and HfO x for amorphous InGaZnO thin-film transistors

To strengthen the downscaling potential of top-gate amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), the ultra-thin gate insulator (GI) was comparatively implemented using the atomic-layer-deposited (ALD) AlO x and HfO x . Both kinds of high-k GIs exhibit good insulating properties even with the physical thickness thinning to 4 nm. Compared to the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs with 4 nm AlO x GI, the 4 nm HfO x enables a larger GI capacitance, while the HfO x -gated TFT suffers higher gate leakage current and poorer subthreshold slope, respectively originating from the inherently small band offset and the highly defective interface between a-IGZO and HfO x . Such imperfect a-IGZO/HfO x interface further causes noticeable positive bias stress instability. Both ALD AlO x and HfO x were found to react with the underneath a-IGZO channel to generate the interface defects, such as metal interstitials and oxygen vacancies, while the ALD process of HfO x gives rise to a more severe reduction of a-IGZO. Moreover, when such a defective interface is covered by the top gate, it cannot be readily restored using the conventional oxidizing post-treatments and thus desires the reduction-resistant pre-treatments of AOSs.

High-Performance Top-Gated and Double-Gated Oxide–Semiconductor Ferroelectric Field-Effect Transistor Enabled by Channel Defect Self-Compensation Effect

In this article, we demonstrate a low-thermal budget defect-engineered process to achieve top-gated (TG) oxide–semiconductor ferroelectric field-effect transistors (FeFETs). The demonstrated TG FeFETs, with the channel length scaled down to 40 nm, exhibit a highly stabilized ferroelectric memory window (MW) of 2 V and a high current ON/ OFF ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{6}}$ </tex-math></inline-formula> . This is achieved by an engineered InGaZnOx (IGZO) and InSnOx (ITO) heterojunction channel that produces the defect self-compensation effect to passivate the intrinsic oxygen-deficient defects, existing in the indium-gallium-zinc-oxide (IGZO) channel interface and bulk. Effective interface/bulk defects passivation with good control of defect-induced channel carrier concentration has been notoriously difficult to achieve. Hence, realizing performant TG oxide-based FeFETs with back-end-of-line (BEOL) thermal budget constraints remains a fundamental challenge. Our study shows that heterojunction channel engineering on FETs and FeFETs can be a reliable solution to overcome this challenge. With such a technique, we can now enable double-gated (DG) ITO–IGZO FeFET and FETs. Such devices can enable BEOL-compatible reconfigurable nonvolatile logic switches that provide extremely low off-state leakage, high switch conductance ratio, and memory read-write disturb-free features.

Organic/Inorganic Hybrid Top-Gate Transistors with Ultrahigh Electron Mobility via Enhanced Electron Pathways

The top-gate structure is currently adopted in various flat-panel displays because of its diverse advantages such as passivation from the external environment and process compatibility with industries. However, the mobility of the currently commercialized top-gate oxide thin-film transistors (TFTs) is insufficient to drive ultrahigh-resolution displays. Accordingly, this work suggests metal-capped Zn-Ba-Sn-O transistors with top-gate structures for inducing mobility-enhancing effects. The fabricated top-gate device contains para-xylylene (PPx), which is deposited by a low-temperature chemical vapor deposition (CVD) process, as a dielectric layer and exhibits excellent interfacial and dielectric properties. A technology computer-aided design (TCAD) device simulation reveals that the mobility enhancement in the Al-capped (Zn,Ba)SnO3 (ZBTO) TFT is attributed not only to the increase in the electron concentration, which is induced by band engineering due to the Al work function but also to the increased electron velocity due to the redistribution of the lateral electric field. As a result, the mobility of the Al-capped top-gate ZBTO device is 5 times higher (∼110 cm2/Vs) than that of the reference device. These results demonstrate the applicability of top-gate oxide TFTs with ultrahigh mobility in a wide range of applications, such as for high-resolution, large-area, and flexible displays.

Trench-Structured High-Current-Driving Aluminum-Doped Indium–Tin–Zinc Oxide Semiconductor Thin-Film Transistor

This letter presents a thin-film transistor architecture, in which a “trench” is introduced between the source and drain electrode to enhance current flow. The top-gate top-contact oxide Trench thin-film transistor has a superior on-current per width of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$27.7~\mu \text{A}/ \mu \text{m}$ </tex-math></inline-formula> at a drain voltage of 4.1 V. It also has a good subthreshold swing of 0.122 V/dec and turn-on voltage of −0.4 V. This study explores the operating mechanism of the high-current-driving Trench oxide thin-film transistor.

48.3: Variable Top Gate Oxide TFT Structures for Premium High‐end Display with Process Simplicity and Device Stability

48.3: Variable Top Gate Oxide TFT Structures for Premium High‐end Display with Process Simplicity and Device Stability

Scaling study of contact operation at constant current in self-aligned top-gated oxide semiconductor field-effect transistors

An extraction framework that can precisely reflect the metal-semiconductor contact behavior is developed for self-aligned top-gated oxide semiconductor field-effect transistors (SA-TG OS FETs). In contrast to the conventional transfer length method, where the extraction is performed at a constant drain voltage condition, an improved constant current scheme, resilient to bias-dependent series resistance, is employed to enhance the extraction accuracy. This technique enables one to unveil the underlying device physics at the metal-OS interface under top-gated operation. Furthermore, the resistance of contact and extension regions can be accurately differentiated by exploiting the extraction results from the three-terminal FETs and two-terminal resistors using the present framework. Moreover, the significant role of the specific contact resistivity at the metal-OS interface is highlighted as the dominating factor that detrimentally affects the electrical performance of OS FETs.

Mobility Enhancement and Abnormal Humps in Top-Gate Self-Aligned Double-Layer Amorphous InGaZnO TFTs

The mobility enhancement and the positive bias stress of top-gate self-aligned TFTs using the a-IGZO channel with a front barrier are investigated. The a-IGZO front barrier can keep electrons in the a-IGZO channel away from the top-gate oxide to significantly enhance the electron mobility at the top gate operation. The parasitic channel induces a hump in the transfer characteristics. The positive bias stress shifts the hump to the negative voltage abnormally. The H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O in the polymer film on array layer is responsible for the abnormal shift. The H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O diffuses into the top-gate insulator and is electrolyzed to create H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> , which forms a parasitic channel with a negative shift of threshold voltage, leading to the abnormal hump. The abnormal humps are increasingly significant with the increasing channel width and the decreasing channel length. The channel width dependence on positive bias stress is due to the inverse narrow width effect caused by the fringe electric field. The channel length dependence on positive bias stress is due to the H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> diffusion toward the center of the parasitic channel from both the source and drain sides.

Remarkably stable high mobility self-aligned oxide TFT by investigating the effect of oxygen plasma time during PEALD of SiO2 gate insulator

Oxide thin-film transistors (TFTs) should be manufactured with high mobility and stability based on a self-aligned top-gate structure to drive high-end displays. In this study, the effect of oxygen plasma time over one cycle of plasma-enhanced atomic layer deposition (PEALD) SiO2 on the properties of top-gate oxide TFTs was investigated systemically. The subsurface reaction of oxygen plasma causes a difference in oxygen vacancy (Vo). In addition, hydrogen incorporation also differs according to plasma time. Considering Vo and hydrogen are donors, tendency of electric properties could be explained. These surface reactions and atomic incorporation also induce differences in the positive bias temperature stress (PBTS) stability. Based on oxygen plasma time of 2.0 s, a positive shift in threshold voltage (Vth) due to interfacial degradation was observed when the plasma was longer, while an abnormal negative shift due to H+ drift was observed when it was shorter. When the oxygen plasma time is 2.0 s, the TFT was free from the deterioration of the interface and SiO2. Based on this condition, a self-aligned TFT with superior performance including a high mobility of 31.1 cm2/Vs, positive Vth and high stability of 0.016 V shifting during the PBTS was fabricated successfully.

P‐1.3: Novel Top Gate Oxide Thin Film Transistor: With Top Light Shielding Metal Structure

SID Symposium Digest of Technical PapersVolume 52, Issue S2 p. 692-692 Poster Session: P-1: AMD P-1.3: Novel Top Gate Oxide Thin Film Transistor: With Top Light Shielding Metal Structure Macai Lu, Macai Lu Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorNian Liu, Nian Liu Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorLu Gao, Lu Gao Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorXueru Mei, Xueru Mei Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorMinggang Liu, Minggang Liu Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorZhuhui Li, Zhuhui Li Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorZhengyu Feng, Zhengyu Feng Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorJiangbo Yao, Jiangbo Yao Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this author Macai Lu, Macai Lu Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorNian Liu, Nian Liu Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorLu Gao, Lu Gao Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorXueru Mei, Xueru Mei Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorMinggang Liu, Minggang Liu Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorZhuhui Li, Zhuhui Li Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorZhengyu Feng, Zhengyu Feng Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this authorJiangbo Yao, Jiangbo Yao Advance Display Research Center, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, Guangdong, ChinaSearch for more papers by this author First published: 26 August 2021 https://doi.org/10.1002/sdtp.15251AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat No abstract is available for this article. Volume52, IssueS2International Conference on Display Technology (ICDT 2021)August 2021Pages 692-692 RelatedInformation

Stability enhancement of top-gate self-aligned tin-doped indium gallium oxide thin film transistor by low temperature annealing

Top-gate self-aligned IGTO TFTs were used as an example to study the contradiction of uniformity and PBTS stability when developing TFT with high mobility. High intrinsic carrier concentration restricted the tuning of SiO2 deposition. To ensure the uniformity, relatively higher power was employed for GI deposition to reduce donor-type oxygen vacancies. Deep electron traps formed by excess oxygen lead to poor PBTS stability. The PBTS stability was improved without deterioration of uniformity by introducing low temperature (200 °C) annealing, to control hydrogen diffusion from ILD layer which would passivate the electron traps.

The Display Week 2021 Symposium Preview

The Display Week 2021 Symposium Preview

Interfacial Oxidized Gate Insulators for Low-Power Oxide Thin-Film Transistors

Low power consumption is essential for wearable and internet-of-things applications. An effective way of reducing power consumption is to reduce the operation voltage using a very thin and high-dielectric gate insulator. In an oxide thin-film transistor (TFT), the channel layer is an oxide material in which oxygen reacts with metal to form a thin insulator layer. The interfacial oxidation between the gate metal and In–Ga–Zn oxide (IGZO) was investigated with Al, Ti, and Mo. Positive bias was applied to the gate metal for enhanced oxygen diffusion since the migration of oxygen is an important factor in interfacial oxidation. Through interfacial oxidation, a top-gate oxide TFT was developed with low source–drain voltages below 0.5 V and a gate voltage swing less than 1 V, which provide low power consumption.

Self-Aligned Top-Gate Amorphous Zinc-Tin Oxide Thin-Film Transistor With Source/Drain Regions Doped by Al Reaction

A self-aligned fabrication process for top-gate amorphous zinc-tin oxide (a-ZTO) thin-film transistors (TFTs) is developed, in which the source/drain (S/D) doping is realized through depositing a thin aluminum (Al) film on S/D regions and performing a thermal annealing. Results indicate that a chemical oxidation-reduction reaction between Al and a-ZTO films takes place during the thermal annealing process, and shallow donors of oxygen vacancies and metal tin (Sn) interstitials are thus generated. The formed S/D regions have a high carrier concentration over 1 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">20</sup> cm $^{-3}$ , low sheet resistance of 0.57 k Ω/sq, and high thermal stability even in oxygen ambient. The fabricated a-ZTO TFTs exhibit excellent electrical performances, including a low channel-width-normalized S/D resistance of about 7.05 Ω cm, a high field-effect mobility of 15.7 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, a high on/off current ratio of over $10 ^{8}$ , and near-zero turn-on voltage. Moreover, good electrical stability with less than 0.2-V threshold voltage shift under ±30-V gate bias stresses is also achieved.

Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric.

For high-speed and large-area active-matrix displays, metal-oxide thin-film transistors (TFTs) with high field-effect mobility, stability, and good uniformity are essential. Moreover, reducing the RC delay is also important to achieve high-speed operation, which is induced by the parasitic capacitance formed between the source/drain (S/D) and the gate electrodes. From this perspective, self-aligned top-gate oxide TFTs can provide advantages such as a low parasitic capacitance for high-speed displays due to minimized overlap between the S/D and the gate electrodes. Here, we demonstrate self-aligned top-gate oxide TFTs using a solution-processed indium-gallium-zinc-oxide (IGZO) channel and crosslinked poly(4-vinylphenol) (PVP) gate dielectric layers. By applying a selective Ar plasma treatment on the IGZO channel, low-resistance IGZO regions could be formed, having a sheet resistance value of ~20.6 kΩ/sq., which can act as the homojunction S/D contacts in the top-gate IGZO TFTs. The fabricated self-aligned top-gate IGZO TFTs exhibited a field-effect mobility of 3.93 cm2/Vs and on/off ratio of ~106, which are comparable to those fabricated using a bottom-gate structure. Furthermore, we also demonstrated self-aligned top-gate TFTs using electrospun indium-gallium-oxide (IGO) nanowires (NWs) as a channel layer. The IGO NW TFTs exhibited a field-effect mobility of 0.03 cm2/Vs and an on/off ratio of >105. The results demonstrate that the Ar plasma treatment for S/D contact formation and the solution-processed PVP gate dielectric can be implemented in realizing self-aligned top-gate oxide TFTs.