Top-gated Graphene Field-effect Transistors Research Articles

Study of High-Energy Proton Irradiation Effects in Top-Gate Graphene Field-Effect Transistors

In this article, the effects of high-energy proton irradiation on top-gate graphene field-effect transistors (GFETs) were investigated by using 20 MeV protons. The basic electrical parameters of the top-gate GFETs were measured before and after proton irradiation with a fluence of 1 × 1011 p/cm2 and 5 × 1011 p/cm2, respectively. Decreased saturation current, increased Dirac sheet resistance, and negative drift in the Dirac voltage in response to proton irradiation were observed. According to the transfer characteristic curves, it was found that the carrier mobility was reduced after proton irradiation. The analysis suggests that proton irradiation generates a large net positive charge in the gate oxide layer, which induces a negative drift in the Dirac voltage. Introducing defects and increased impurities at the gate oxide/graphene interface after proton irradiation resulted in enhanced Coulomb scattering and reduced mobility of the carriers, which in turn affects the Dirac sheet resistance and saturation current. After annealing at room temperature, the electrical characteristics of the devices were partially restored. The results of the technical computer-aided design (TCAD) simulation indicate that the reduction in carrier mobility is the main reason for the degradation of the electrical performance of the device. Monte Carlo simulations were conducted to determine the ionization and nonionization energy losses induced by proton incidence in top-gate GFET devices. The simulation data show that the ionization energy loss is the primary cause of the degradation of the electrical performance.

TETHYS: A simulation tool for graphene hydrodynamic models

We present a simulation tool, TETHYS (i.e., Two-dimensional Emitter of THz, Hydrodynamic Simulation), developed with the aim of studying hydrodynamic models for electronic transport in graphene, being particularly tailored for the simulation of the configuration of top-gated graphene field-effect transistors (GFET) near room temperature. We present the model governing the system and briefly discuss its validity and physical parameters; then we proceed to discuss the algorithms and numerical methods used in its implementation, namely, two-step Richtmyer and weighted forward-time centred-space schemes, which address the hyperbolic and parabolic parts of the model, respectively. An abridged usage guide and description of the output are also provided, as well as two illustrative simulation cases: the Dyakonov–Shur instability and the boundary layer of pulsatile electric flow. The simulation program here brought forward is uncomplicated and lightweight, yet robust and accurate, having a wide variety of applicable scenarios and configurations to explore. Program summaryProgram Title: TETHYSCPC Library link to program files:https://doi.org/10.17632/s28zwgpnpw.1Developer's repository link:github.com/pcosme/TETHYS-Graphene-Hydrodynamic-SimulationLicensing provisions: MITProgramming language: C++Nature of problem: The main objective of this code is to simulate and analyse the electronic conduction on gated (mono-layer) graphene resorting to a hydrodynamic model [1]. Note that, given the Dirac-like dispersion relation of such material, the mass of the carriers is ill-defined; and, in fact, the mass of the fluid element varies with the number density, which sets this system apart from other 2D electron fluids [2]. The model assumes enough doping, so that only one kind of carriers, electrons or holes, participates in the dynamics of the system. Moreover, the simulation is limited to the fully degenerate limit.Thus, these assumptions correspond to the situation of a regular GFET and this application can be used to explore atypical phenomena arising from the effects of uniform and static magnetic field and Hall viscosity, and even spatially non-uniform gate capacitance.Furthermore, this software was designed with the intent of examining unstable nonlinear modes that may lead to the emission of radiation in the THz range [3].Solution method: The fluid equations (continuity, momentum and energy transport) are solved with a split-operator technique, with a second-order finite-volume Lax–Wendroff method [4] for the hyperbolic part and a forward-time centred-space of second-order stencil to tackle the dissipation and heat diffusion. That is, the fields of number density, velocity/momentum density and temperature are calculated over a rectangular grid and stored at a HDF5 file for further processing.Then, the obtained field profiles are used to compute the relevant macroscopic electronic quantities, such as drain-to-source current or dissipated power, and, particularly, the electric dipole moment of the charge distribution, which can subsequently be used to characterize the emitted far-field radiation. This is mostly done by numerically integrating the data in space, with the necessary time derivatives obtained by Gaussian convolution.

Electric-Field Induced Doping Polarity Conversion in Top-Gated Transistor Based on Chemical Vapor Deposition of Graphene

The top-gated graphene field effect transistor (GFET) with electric-field induced doping polarity conversion has been demonstrated. The polarity of channel conductance in GFET can be transition from p-type to n-type through altering the gate electric field scanning range. Further analysis indicates that this complementary doping is attributed to the charge exchange between graphene and interface trap sites. The oxygen vacancies in Al2O3filmare are considered to be the origin of the trap sites. The trapping–detrapping process, which may be tuned by the electric field across the metal/oxide/graphene gate stack, could lead to the changing of the intrinsic electric property of graphene. This study promises to produce the complementary p- and n-type GFET for logic applications.

Enhanced High-Frequency Performance of Top-Gated Graphene FETs Due to Substrate- Induced Improvements in Charge Carrier Saturation Velocity

The high-frequency performance of top-gated graphene field-effect transistors (GFETs) depends to a large extent on the saturation velocity of the charge carriers, a velocity limited by inelastic scattering by surface optical phonons from the dielectrics surrounding the channel. In this work, we show that, by simply changing the graphene channel surrounding dielectric with a material having higher optical phonon energy, one could improve the transit frequency and maximum frequency of oscillation of GFETs. We fabricated GFETs on conventional SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si substrates by adding a thin Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> interfacial buffer layer on top of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si substrates, a material with about 30% higher optical phonon energy than that of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and compared performance with that of GFETs fabricated without adding the interfacial layer. From S-parameter measurements, a transit frequency and a maximum frequency of oscillation of 43 and 46 GHz, respectively, were obtained for GFETs on Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> with 0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> gate length. These values are approximately 30% higher than those for state-of-the-art GFETs of the same gate length on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . For relating the improvement of GFET high-frequency performance to improvements in the charge carrier saturation velocity, we used standard methods to extract the charge carrier velocity from the channel transit time. A comparison between two sets of GFETs with and without the interfacial Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layer showed that the charge carrier saturation velocity had increased from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\cdot 10^{{7}}$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\cdot 10^{{7}}$ </tex-math></inline-formula> cm/s.

Advantages of a buried-gate structure for graphene field-effect transistor

Graphene field effect transistors (GFETs) with top-gate and back-gate structures have been extensively used without much consideration for compatibility with graphene. A comparative study of the electrical characteristics of buried-gate GFETs and top-gate GFETs revealed that the performance of buried-gate GFETs is drastically enhanced by having a better gate controllability, achieving three times higher field effect mobility (∼3000 cm2 V−1 s−1) than top-gate GFETs with on/off ratio ∼10. Carrier scattering was also substantially improved by minimizing the fringing field effect, which is found to be the origin of high series resistance in top-gate GFETs. Moreover, we showed by electromagnetic (EM) simulation that the electric field distribution inside the transistors is more uniform at the buried-gate GFETs than the top-gate GFETs.

Spray-On Liquid-Metal Electrodes for Graphene Field-Effect Transistors.

Advancements in flexible circuit interconnects are critical for widespread adoption of flexible electronics. Non-toxic liquid-metals offer a viable solution for flexible electrodes due to deformability and low bulk resistivity. However, fabrication processes utilizing liquid-metals suffer from high complexity, low throughput, and significant production cost. Our team utilized an inexpensive spray-on stencil technique to deposit liquid-metal Galinstan electrodes in top-gated graphene field-effect transistors (GFETs). The electrode stencils were patterned using an automated vinyl cutter and positioned directly onto chemical vapor deposition (CVD) graphene transferred to polyethylene terephthalate (PET) substrates. Our spray-on method exhibited a throughput of 28 transistors in under five minutes on the same graphene sample, with a 96% yield for all devices down to a channel length of 50 μm. The fabricated transistors possess hole and electron mobilities of 663.5 cm2/(V·s) and 689.9 cm2/(V·s), respectively, and support a simple and effective method of developing high-yield flexible electronics.

Theoretical Considerations on the Optimal Performance of Sub-100 Nanometer Top-Gated Graphene Field-Effect Transistors

The operation and performance of top-gated sub-100 nanometer graphene channel field-effect transistors were investigated. The device model is designed for graphene with a narrow energy band gap epitaxially grown on the SiC substrate. The issue of graphene-metallic lead coupling is appropriately taken into account. By assuming the graphene-metal physisorption contact, a self-consistent calculation reproduces two regions of high carrier density at the ends of the graphene channels underneath the metallic leads according to the charge transferred effect between the metallic lead surface and graphene. The charge carrier densities in these source and drain regions, however, are not pinned, but vary with respect to the drain and gate voltages. It is shown that, in general, the graphene channel supports the ambipolar characteristics for all device samples, but for the samples with the channels shorter than 40 nm, the current-voltage characteristic takes the exponential law. Particularly, the current saturation with a rather small output conductance of 126 S/m was observed in a sufficiently large range of drain voltage due to the dominance of the thermionic emission and conventional tunneling mechanisms to the band-to-band tunneling. A rough assessment of the device performance was also carried out. It reveals an extremely high cutoff frequency in the order of $$10^3\hbox { GHz}$$ and a linear scaling rule for transistors with the channel length longer than 40 nm. The behaviour and magnitude of these quantities are consistent with an experimental study of sub-100 nm devices fabricated using the self-alignment technique.

A High-Performance Top-Gated Graphene Field-Effect Transistor with Excellent Flexibility Enabled by an iCVD Copolymer Gate Dielectric.

A high-performance top-gated graphene field-effect transistor (FET) with excellent mechanical flexibility is demonstrated by implementing a surface-energy-engineered copolymer gate dielectric via a solvent-free process called initiated chemical vapor deposition. The ultrathin, flexible copolymer dielectric is synthesized from two monomers composed of 1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane and 1-vinylimidazole (VIDZ). The copolymer dielectric enables the graphene device to exhibit excellent dielectric performance and substantially enhanced mechanical flexibility. The p-doping level of the graphene can be tuned by varying the polar VIDZ fraction in the copolymer dielectric, and the Dirac voltage (VDirac ) of the graphene FET can thus be systematically controlled. In particular, the VDirac approaches neutrality with higher VIDZ concentrations in the copolymer dielectric, which minimizes the carrier scattering and thereby improves the charge transport of the graphene device. As a result, the graphene FET with 20 nm thick copolymer dielectrics exhibits field-effect hole and electron mobility values of over 7200 and 3800 cm2 V-1 s-1 , respectively, at room temperature. These electrical characteristics remain unchanged even at the 1 mm bending radius, corresponding to a tensile strain of 1.28%. The formed gate stack with the copolymer gate dielectric is further investigated for high-frequency flexible device applications.

Charge carrier velocity in graphene field-effect transistors

To extend the frequency range of transistors into the terahertz domain, new transistor technologies, materials, and device concepts must be continuously developed. The quality of the interface between the involved materials is a highly critical factor. The presence of impurities can degrade device performance and reliability. In this paper, we present a method that allows the study of the charge carrier velocity in a field-effect transistor vs impurity levels. The charge carrier velocity is found using high-frequency scattering parameter measurements followed by delay time analysis. The limiting factors of the saturation velocity and the effect of impurities are then analysed by applying analytical models of the field-dependent and phonon-limited carrier velocity. As an example, this method is applied to a top-gated graphene field-effect transistor (GFET). We find that the extracted saturation velocity is ca. 1.4×107 cm/s and is mainly limited by silicon oxide substrate phonons. Within the considered range of residual charge carrier concentrations, charged impurities do not limit the saturation velocity directly by the phonon mechanism. Instead, the impurities act as traps that emit charge carriers at high fields, preventing the current from saturation and thus limiting power gain of the GFETs. The method described in this work helps to better understand the influence of impurities and clarifies methods of further transistor development. High quality interfaces are required to achieve current saturation via velocity saturation in GFETs.

Atomic-Layer-Deposition Growth of an Ultrathin HfO2 Film on Graphene.

Direct growth of an ultrathin gate dielectric layer with high uniformity and high quality on graphene remains a challenge for developing graphene-based transistors due to the chemically inert surface properties of graphene. Here, we develop a method to realize atomic-layer-deposition (ALD) growth of an ultrathin high-κ dielectric layer on graphene through premodifying the graphene surface using electron beam irradiation. An amorphous carbon layer induced by electron beam scanning is formed on graphene and then acts as seeds for ALD growth of high-κ dielectrics. A uniform HfO2 layer with an equivalent oxide thickness of 1.3 nm was grown as a gate dielectric for top-gate graphene field-effect transistors (FETs). The achieved gate capacitance is up to 2.63 μF/cm2, which is the highest gate capacitance on a graphene solid-state device to date. In addition, the fabricated top-gate graphene FETs present a high carrier mobility of up to 2500 cm2/(V·s) and a negligible gate leakage current of down to 0.1 mA/cm2, showing that the ALD-grown HfO2 dielectric layer is highly uniform and of very high quality.

Microwave characterization of graphene field effect transistors on lithium niobate ferroelectric substrates

In this paper we discuss our recent microwave measurements on a graphene transistor fabricated on lithium niobate (LiNbO3) substrates. Top gated graphene field-effect transistors (G-FETs) were fabricated on LiNbO3 substrates and their high frequency operation were analyzed. The measured cutoff frequency fT as a function of gate voltage derived from S parameters is found to be proportional to the G-FET’s transconductance. An intrinsic cut off frequency up to 10 GHz was measured for a 600 nm gate graphene transistor.

Top-gated graphene field-effect transistors by low-temperature synthesized SiNx insulator on SiC substrates

Top-gated devices made from an epitaxial graphene film on a 4H-SiC substrate were fabricated. Atomic force microscopy and Raman spectroscopy results showed that a large-scale highly uniform monolayer graphene film was synthesized on the SiC substrate. A SiNx passivation film was deposited on a SiC graphene device as a top gate insulator by catalytic chemical-vapor deposition (Cat-CVD) below 65 °C. After the top gate electrode was formed on the SiNx film, no leakage current flowed between the gate and source electrodes. The transport characteristics showed clear ambipolar characteristics from 8 to 280 K, and the temperature dependences of the conductance and field-effect mobility of the devices implied that monolayer graphene devices can be successfully fabricated. Moreover, the position of the charge neutrality point after SiNx deposition was around 0 V, indicating p-doping characteristics. These results indicate that SiNx films synthesized by Cat-CVD can be used as gate insulators and that the carrier type may be controlled by adjusting the deposition conditions.

Electrical Characteristics of Top-Gated Graphene Field Effect Transistors Fabricated on Stainless Steel (STS) Substrate.

Top-gated Graphene transistors with Al2O3 gate-dielectric on the flexible stainless steel substrate have been demonstrated. Graphene was synthesized on copper foil using a chemical vapor deposition method and transferred onto the stainless steel substrate by wet transfer technique. The stainless steel substrate was polished by chemical mechanical polishing method and the spin-on-glass layer was coated on the surface to improve the surface roughness. The average surface roughness R(a) was as low as 5.9 nm from the AFM measurement. The measured hole and electron mobilities from the current-voltage characteristics at room temperature were calculated as high as 310 and 45 cm2/Vs, respectively. In addition, the effect of surrounding temperature up to 355 K on the electrical variations was investigated. The mobility was inversely proportional to the temperature with negligible hysteresis where the temperature coefficient was calculated as low as -0.65 %/K.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Effect of ferroelectric substrate on carrier mobility in graphene field-effect transistors

Effect of LiNbO3 ferroelectric substrate on the carrier mobility in top gated graphene field-effect transistors (G-FETs) is demonstrated. It is shown that, at the same residual concentration of the charge carriers, the mobility in the G-FETs on the LiNbO3 substrate is higher than that on the SiO2/Si substrate. The effect is associated with reduction of Coulomb scattering via screening the charged impurity field by the field induced in the ferroelectric substrate, but significant only for mobilities below 1000 cm2/V s. Raman spectra analysis and correlations established between mobility and microwave loss tangent of the Al2O3 gate dielectric indicate that the charged impurities are located predominantly at the gate dielectric and/or at the gate dielectric/graphene interface and are likely associated with oxygen vacancies.

(Invited) Excellent Wetting Behavior of Yttria on 2D Materials

A high quality yttrium oxide (yttria, Y2O3) dielectric has been grown on different carbon derivatives materials (carbon nanotubes, exfoliated graphene, chemical vapor deposition graphene).1-5 This opens the possibility to use such dielectric for the fabrication of graphene devices.4-5 In this talk, the good wettability of Y2O3 on graphene is demonstrated using various surface science methods. Furthermore, the favorable wetting behavior of yttria is exploited as an effective seeding layer for atomic layer deposition of Al2O3 on graphene.6 Moreover, we investigated the interface between Y2O3 and the transition metal dichalcogenide MoS2 as well as on highly ordered pyrolytic graphite (HOPG). The growth of the yttria film was monitored in-situ by monochromatic X-ray photoelectron spectroscopy and scanning tunneling microscopy (XPS and STM). Depositing yttrium metal results in a chemical interaction between the adlayer and the substrate. However, no indication of chemical interaction was detected for the Y2O3 growth, formed by evaporating yttrium in background O2 environment. This is due to the initial formation of Y-O bonds, before the weak Y-MoS2 and Y-C interaction occurs. The STM results indicate the formation of a uniform dielectric film on both MoS2 and HOPG surfaces, confirming the previous findings on graphene. In conclusions, our results reveal that the underlying MoS2and graphene remains intact following yttria seed deposition. Photoemission measurements of the graphene/oxide contacts indicate n-type doping of graphene with different doping levels caused by the charge transfer at the interfaces. This work was supported in part by the Southwest Academy on Nanoelectronics sponsored by the Nanoelectronic Research Initiative. -- [1] R. Addou, A. Dahal, and M. Batzill Growth of a Two-Dimensional Dielectric Monolayer on Quasi-Freestanding Graphene. Nature Nanotechnol. 8, 41-45 (2013). [2] A. Dahal, H. Coy-Diaz H, R. Addou, J. Lallo, E. Sutter, and M. Batzill Preparation and Characterization of Ni(111)/Graphene/Y2O3(111) Heterostructures. J. Appl. Phys. 113, 194305 (2013). [3] A. Dahal, R. Addou, H. Coy-Diaz, J. Lallo, and M. Batzill. Charge Doping of Graphene in Metal/Graphene/Dielectric Sandwich Structure Evaluated by C-1s Core Level Photoemission Spectroscopy. APL Mater. 1, 042107 (2013). [4] H. Xu, Z. Zhang, Z. Wang, S. Wang, X. Liang, and L. M. Peng Quantum capacitance limited vertical scaling of graphene field- effect transistor. ACS Nano 5, 2340–2347 (2011). [5] H. Xu, Z. Zhang, H. Xu, Z. Wang, S. Wang, and L. M. Peng Top-gated graphene field-effect transistors with high normalized transconductance and designable Dirac point voltage. ACS Nano 5, 5031–5037 (2011). [6] A. Dahal, R. Addou, A. Azcatl, H. Coy-Diaz, N. Lu, X. Peng, F. de Dios, J. Kim, M. J. Kim, R. M. Wallace, and M. Batzill. Seeding Atomic Layer Deposition of Alumina on Graphene with Yttria. ACS Appl. Mater. Interfaces 7, 2082-2087 (2015).

Extraction of the Interface State Density of Top-Gate Graphene Field-Effect Transistors

Novel electrical measurement method, discharge current analysis (DCA), is introduced to extract the density and energy distribution of charge traps at the dielectric interface of top-gate graphene field-effect transistors. Using DCA method, the highest charge trap density <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 10^{13}$ </tex-math></inline-formula> (cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}\cdot $ </tex-math></inline-formula> eV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-1}$ </tex-math></inline-formula> ) is extracted at Fermi level <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 0.4$ </tex-math></inline-formula> eV. This is the first quantitative estimation of trap density at a specific Fermi level of graphene.

Dirac point and transconductance of top-gated graphene field-effect transistors operating at elevated temperature

Top-gated graphene field-effect transistors (GFETs) have been fabricated using bilayer epitaxial graphene grown on the Si-face of 4H-SiC substrates by thermal decomposition of silicon carbide in high vacuum. Graphene films were characterized by Raman spectroscopy, Atomic Force Microscopy, Scanning Tunnelling Microscopy, and Hall measurements to estimate graphene thickness, morphology, and charge transport properties. A 27 nm thick Al2O3 gate dielectric was grown by atomic layer deposition with an e-beam evaporated Al seed layer. Electrical characterization of the GFETs has been performed at operating temperatures up to 100 °C limited by deterioration of the gate dielectric performance at higher temperatures. Devices displayed stable operation with the gate oxide dielectric strength exceeding 4.5 MV/cm at 100 °C. Significant shifting of the charge neutrality point and an increase of the peak transconductance were observed in the GFETs as the operating temperature was elevated from room temperature to 100 °C.

Antenna-integrated 0.6 THz FET direct detectors based on CVD graphene.

We present terahertz (THz) detectors based on top-gated graphene field effect transistors (GFETs) with integrated split bow-tie antennas. The GFETs were fabricated using graphene grown by chemical vapor deposition (CVD). The THz detectors are capable of room-temperature rectification of a 0.6 THz signal and achieve a maximum optical responsivity better than 14 V/W and minimum optical noise-equivalent power (NEP) of 515 pW/Hz(0.5). Our results are a significant improvement over previous work on graphene direct detectors and are comparable to other established direct detector technologies. This is the first time room-temperature direct detection has been demonstrated using CVD graphene, which introduces the potential for scalable, wafer-level production of graphene detectors.

High performance graphene field effect transistors on an aluminum nitride substrate with high surface phonon energy

We demonstrate top-gate graphene field effect transistors (FETs) on an aluminum nitrite (AlN) substrate with high surface phonon energy. Electrical transport measurements reveal significant improvement of the carrier mobility of graphene FETs on AlN compared to those on SiO2. This is attributed to the suppression of surface phonon scattering due to the high surface phonon energy of the AlN substrate. The RF cut-off frequency of the graphene FET is also greatly increased when the AlN substrate is used. AlN can easily be formed on a Si or SiO2 substrate using a standard semiconductor process and thus provides a practical way to improve the performance of graphene FETs.