Top-gate Field-effect Transistors Research Articles

Top-Gated Graphene Field-Effect Transistors with High Normalized Transconductance and Designable Dirac Point Voltage

High-performance graphene field-effect transistors (G-FETs) are fabricated with carrier mobility of up to 5400 cm(2)/V·s and top-gate efficiency of up to 120 (relative to that of back gate with 285 nm SiO(2)) simultaneously through growing high-quality Y(2)O(3) gate oxide at high oxidizing temperature. The transconductance normalized by dimension and drain voltage is found to reach 7900 μF/V·s, which is among the largest of the published graphene FETs. In an as-fabricated graphene FET with a gate length of 310 nm, a peak transconductance of 0.69 mS/μm is realized, but further improvement is seriously hindered by large series resistance. Benefiting from highly efficient gate control over the graphene channel, the Dirac point voltage of the graphene FETs is shown to be designable via simply selecting a gate metal with an appropriate work function. It is demonstrated that the Dirac point voltage of the graphene FETs can be adjusted from negative to positive, respectively, via changing the gate material from Ti to Pd.

CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors

Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL−1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors.

Large-Area Synthesis of Graphene by Chemical Vapor Deposition and Transfer-Free Fabrication of Field-Effect Transistors

Graphene was synthesized on SiO2/Si wafers as large as 200 mm in diameter by thermal chemical vapor deposition (CVD) using Fe or Cu films as catalyst, and top-gated field-effect transistors (FETs) were fabricated directly on the wafer using a graphene-transfer-free process. For transistor fabrication, graphene was synthesized on patterned Fe films. The iron was subsequently etched after both ends of the graphene were fixed by source and drain electrodes (Au/Ti), resulting in the graphene channels bridging the electrodes all over the wafer. Top-gated FETs were then formed after covering the channels with HfO2 by the atomic layer deposition (ALD) method. The fabricated transistors exhibit ambipolar behavior and can sustain a high-density current. Dependence of graphene growth on catalyst types and various growth parameters was also investigated.

Low-Phase-Noise Graphene FETs in Ambipolar RF Applications

In this letter, we present both the 1/f noise and phase noise performance of top-gated epitaxial graphene field-effect transistors (FETs) in nonlinear circuit applications for the first time. In the case of frequency doublers, the fundamental signal is suppressed by 25 dB below the second harmonic signal. With a phase noise of -110 dBc/Hz measured at a 10-kHz offset, a carrier-to-noise degradation (ΔCNR) of 6 dB was measured for the frequency doubler. This implies noiseless frequency multiplication without additional 1/f noise upconversion during the nonlinear process. The frequency multiplication was demonstrated above the gigahertz range. The 1/f noise of top-gated epitaxial graphene FETs is comparable or lower than that of exfoliated graphene FETs.

Quantum Capacitance Limited Vertical Scaling of Graphene Field-Effect Transistor

A high-quality Y2O3 dielectric layer has been grown directly on graphene and used to fabricated top-gate graphene field-effect transistors (FETs), and the thickness of the dielectric layer has been reduced continuously down to 3.9 nm with an equivalent oxide thickness (EOT) of 1.5 nm and excellent insulativity. By measuring CV characteristics of two graphene FETs with different gate oxide thicknesses, the oxide capacitance and quantum capacitance are retrieved directly from the experimental CV data without introducing any additional fitting process and parameters, yielding a relative dielectric constant of κ=10 for Y2O3 on graphene and an oxide capacitance of about 2.28 μF/cm2. It is found that for a rather large gate voltage range, this oxide capacitance is comparable and sometimes even larger than the quantum capacitance of graphene. Since the total gate capacitance is determined by the smaller of the oxide and quantum capacitance, our results show that not much further improvement can be gained via further vertical scaling down of the gate oxide, suggesting that Y2O3 may be the ultimate dielectric material for graphene. It is also shown that the Y2O3 gate dielectric layer with EOT of 1.5 nm may also satisfy the ultimate lateral scaling requirement on the gate length of graphene FET and be used effectively to control a graphene FET with a gate length as small as 1 nm.

Controlling contact resistance in top-gate polythiophene-based field-effect transistors by molecular engineering

We report on an effective control of source–drain contact resistance by insertion of a self-assembled monolayer at the metal/semiconductor interface in top-gate staggered polymer field-effect transistors fabricated with poly(2,5-bis(3-tetradecylthiophene-2-yl)thieno[3,2-b]thiophene) (pBTTT). The device performance can be dramatically improved by introducing a fluorinated alkyl-thiol, 1H, 1H, 2H, 2H-perflourodecanethiol (PFDT) on the gold source–drain contacts. The PFDT-induced interface dipole and hydrophobic surface enables both a favourable shift of work function lowering the hole injection barrier via dipole alignment and a large crystal growth of pBTTT film with a unique lamellar morphology near to the contact. The optimized device with PFDT-modified gold contact plus OTS-treated substrate exhibits a high field-effect mobility above 0.4 cm2 V−1 s−1 and low contact resistance of 0.45 MΩ at the gate voltage of −60 V.

HIGH FREQUENCY TOP-GATED GRAPHENE RF AMBIPOLAR FETs USING LARGE-AREA CVD GRAPHENE AND ADVANCED DIELECTRICS

ABSTRACTAmbipolar top-gated field effect transistors (FETs) based on large area Cu catalyzed CVD-grown monolayer graphene interfaced to advanced dielectrics have been constructed and examined both for their material and electrical qualities. Interfacing of the graphene with novel insulators/substrates could be tailored for the particular application and provide for enhanced device functionality. In contrast to graphene FETs using SiO2-based top-gate dielectric, which show asymmetric electron/hole mobility (with larger hole mobility), and Dirac point shifted to positive levels, FETs constructed using advanced AlN show Dirac point almost near neutral levels and near symmetric electron/hole mobility. The DP is shifted likely due to compensation of the intrinsic p-type doping by n-type doping introduced by the AlN deposition and potentially via a contribution of polarization-induced carrier density. Finally, we demonstrate a top-gated graphene FET with the first observation of RF operation with GHz cut-off frequency based on large area CVD graphene.

Fabrication of Carbon Nanotube Field Effect Transistor

The authors review here the growth of carbon nanotube (CNT) by catalytic growth technique and the methods to grow oriented long CNTs with controlled diameters. The process steps for the fabrication of both back and top-gated carbon nanotube field effect transistor (CNFET) are given. We also discuss the techniques for realizing both p and n type of CNT transistors.

Top-Gate Graphene-on-UNCD Transistors with Enhanced Performance

ABSTRACTWe fabricated a number of top-gate graphene field-effect transistors on the ultrananocrystalline diamond (UNCD) – Si composite substrates. Raman spectroscopy, scanning electron microscopy and atomic force microscopy were used to verify the quality of UNCD and graphene device channels. The thermal measurements were carried out with the “hot disk” and “laser flash” methods. It was found that graphene on UNCD devices have increased breakdown current density by ∼50% compared to the reference devices fabricated on Si/SiO2. The relatively smooth surface of UNCD, as compared to other synthetic diamond films, allowed us to fabricate top gate graphene devices with the drift mobility of up to ∼ 2587 cm2V-1s-1.

Doping dependent crystal structures and optoelectronic properties of n-type CdSe:Ga nanowries

Although CdSe nanostructures possess excellent electrical and optical properties, efforts to make nano-optoelectronic devices from CdSe nanostructures have been hampered by the lack of efficient methods to rationally control their structural and electrical characteristics. Here, we report CdSe nanowires (NWs) with doping dependent crystal structures and optoelectronic properties by using gallium (Ga) as the efficient n-type dopant via a simple thermal co-evaporation method. The phase change of CdSe NWs from wurtzite to zinc blende with increased doping level is observed. Systematical measurements on the transport properties of the CdSe:Ga NWs reveal that the NW conductivity could be tuned in a wide range of near nine orders of magnitude by adjusting the Ga doping level and a high electron concentration up to 4.5 × 10(19) cm(-3) is obtained. Moreover, high-performance top-gate field-effect transistors are constructed based on the individual CdSe:Ga NWs by using high-κ HfO(2) as the gate dielectric. The great potential of the CdSe:Ga NWs as high-sensitive photodetectors and nanoscale light emitters is also exploited, revealing the promising applications of the CdSe:Ga NWs in new-generation nano-optoelectronics.

Control of epitaxy of graphene by crystallographic orientation of a Si substrate toward device applications

Graphene is a promising material in next-generation devices. Large-scale epitaxial graphene should be grown on Si substrates to transfer the accumulated technologies to integrated devices. We have for this reason developed epitaxy of graphene on Si (GOS) and device operation of the backgate field-effect transistors (FETs) using GOS has been confirmed. It is demonstrated in this paper that the GOS method enables us to tune the structural and electronic properties of graphene in terms of the crystallographic orientation of the Si substrate. Furthermore, it is shown that the uniformity of the GOS process within a sizable area enables us to reliably fabricate topgate FETs using conventional lithography techniques. GOS can be thus the key material in next-generation devices owing to the tunability of the electronic structure by the crystallographic orientation of the Si substrate.

Top-Gated Graphene Field-Effect Transistors Using Graphene on Si (111) Wafers

In this letter, we report the first experimental demonstration of wafer-scale ambipolar field-effect transistor (FET) on Si (111) substrates by synthesizing a graphene layer on top of 3C-SiC(111)/Si(111) substrates. With lateral scaling of the source-drain distance to 1 μm in a top-gated layout, the ON-state current of 225 μA/μm and peak transconductance of > 40 μS/μm were obtained at Vds = 2 V, which is the highest performance of graphene-on-Si FETs. The peak field-effect mobilities of 285 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs for holes and 175 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs for electrons were demonstrated, which is higher than that of ultra-thin-body SOI (n, p) MOSFETs.

Wafer-scale epitaxial graphene growth on the Si-face of hexagonal SiC (0001) for high frequency transistors

Up to two layers of epitaxial graphene have been grown on the Si-face of 2 in. SiC wafers exhibiting room-temperature Hall mobilities up to 2750 cm2 V−1 s−1, measured from ungated, large, 160×200 μm2 Hall bars, and up to 4000 cm2 V−1 s−1, from top-gated, small, 1×1.5 μm2 Hall bars. The growth process involved a combination of a cleaning step of the SiC in a Si-containing gas, followed by an annealing step in argon for epitaxial graphene formation. The structure and morphology of this graphene has been characterized using atomic force microscopy, high resolution transmission electron microscopy, and Raman spectroscopy. Furthermore, top-gated radio frequency field-effect transistors (rf-FETs) with a peak cutoff frequency fT of 100 GHz for a gate length of 240 nm were fabricated using epitaxial graphene grown on the Si-face of SiC that exhibited Hall mobilities up to 1450 cm2 V−1 s−1 from ungated Hall bars and 1575 cm2 V−1 s−1 from top-gated ones. This is by far the highest cutoff frequency measured from any kind of graphene.

Fabrication of a Graphene Nanoribbon with Electron Beam Lithography Using a XR-1541/PMMA Lift-Off Process

This report covers an effective fabrication method of graphene nanoribbon for top-gated field effect transistors (FETs) utilizing electron beam lithography with a bi-layer resists (XR-1541/poly methtyl methacrylate) process. To improve the variation of the gating properties of FETs, the residues of an e beam resist on the graphene channel are successfully taken off through the combination of reactive ion etching and a lift-off process for the XR-1541 bi-layer. In order to identify the presence of graphene structures, atomic force microscopy measurement and Raman spectrum analysis are performed. We believe that the lift-off process with bi-layer resists could be a good solution to increase gate dielectric properties toward the high quality of graphene FETs.

Single-Hole Charging and Discharging Phenomena in Carbon Nanotube Field-Effect-Transistor-Based Nonvolatile Memory

We have fabricated nonvolatile memory based on top-gated carbon nanotube field-effect transistors (CNTFETs). Two kinds of insulating films, SiNx and SiO2, were deposited to control the hysteresis characteristics after the removal of water molecules around the single-walled CNT channels. The interface between the SiNx and SiO2 films is expected to act as a charge storage node of nonvolatile memory. The fabricated CNTFET-based memory devices clearly exhibited not only a memory effect but also good retention characteristics for charge storage. Furthermore, single-hole charging and discharging phenomena were clearly observed in the CNTFET-based memory devices by reducing the number of carriers trapped in the interface between the SiNx and SiO2 films. These results indicate that the CNTFET-based nonvolatile memory can be potentially used to realize single-electron memory.

Direct-write fabrication of a nanoscale digital logic element on a single nanowire

In this paper we report on the ‘direct-write’ fabrication and electrical characteristics of ananoscale logic inverter, integrating enhancement-mode (E-mode) and depletion-mode(D-mode) field-effect transistors (FETs) on a single zinc oxide (ZnO) nanowire.‘Direct-writing’ of platinum metal electrodes and a dielectric layer is executed onindividual single-crystalline ZnO nanowires using either a focused electron beam(FEB) or a focused ion beam (FIB). We fabricate a top-gate FET structure, inwhich the gate electrode wraps around the ZnO nanowire, resulting in a moreefficient gate response than the conventional back-gate nanowire transistors. ForE-mode device operation, the gate electrode (platinum) is deposited directly ontothe ZnO nanowire by a FEB, which creates a Schottky barrier and in turn afully depleted channel. Conversely, sandwiching an insulating layer between theFIB-deposited gate electrode and the nanowire channel makes D-mode operation possible.Integrated E- and D-mode FETs on a single nanowire exhibit the characteristics of adirect-coupled FET logic (DCFL) inverter with a high gain and noise margin.

Probing top-gated field effect transistor of reduced graphene oxide monolayer made by dielectrophoresis

We demonstrate a top-gated field effect transistor made of a reduced graphene oxide (RGO) monolayer (graphene) by dielectrophoresis. The Raman spectrum of RGO flakes of typical size of 5 μ m × 5 μ m shows a single 2D band at 2687 cm −1, characteristic of single-layer graphene. The two-probe current–voltage measurements of RGO flakes, deposited in between the patterned electrodes with a gap of 2.5 μm using ac dielectrophoresis, show ohmic behavior with a resistance of ∼ 37 k Ω . The temperature dependence of the resistance ( R ) of RGO measured between 305 K and 393 K yields a temperature coefficient of resistance [ d R / d T ] / R ∼ − 9.5 × 1 0 − 4 / K , the same as that of mechanically exfoliated single-layer graphene. The field-effect transistor action was obtained by electrochemical top-gating using a solid polymer electrolyte (PEO+LiClO 4) and Pt wire. The ambipolar nature of graphene flakes is observed up to a doping level of ∼ 6 × 10 12 / cm 2 and carrier mobility of ∼50 cm 2/V s. The source–drain current characteristics show a tendency of current saturation at high source–drain voltage which is analyzed quantitatively by a diffusive transport model.

Thermal shot noise in top-gated single carbon nanotube field effect transistors

The high-frequency transconductance and current noise of top-gated single carbon nanotube transistors have been measured and used to investigate hot electron effects in one-dimensional transistors. Results are in good agreement with a theory of one-dimensional nanotransistor. In particular the prediction of a large transconductance correction to the Johnson–Nyquist thermal noise formula is confirmed experimentally. Experiment shows that nanotube transistors can be used as fast charge detectors for quantum coherent electronics with a resolution of 13 μe/Hz in the 0.2–0.8 GHz band.

Growth and Performance of Yttrium Oxide as an Ideal High-κ Gate Dielectric for Carbon-Based Electronics

High-quality yttrium oxide (Y(2)O(3)) is investigated as an ideal high-kappa gate dielectric for carbon-based electronics through a simple and cheap process. Utilizing the excellent wetting behavior of yttrium on sp(2) carbon framework, ultrathin (about few nm) and uniform Y(2)O(3) layers have been directly grown on the surfaces of carbon nanotube (CNT) and graphene without using noncovalent functionalization layers or introducing large structural distortion and damage. A top-gate CNT field-effect transistor (FET) adopting 5 nm Y(2)O(3) layer as its top-gate dielectric shows excellent device characteristics, including an ideal subthreshold swing of 60 mV/decade (up to the theoretical limit of an ideal FET at room temperature). The high electrical quality Y(2)O(3) dielectric layer has also been integrated into a graphene FET as its top-gate dielectric with a capacitance of up to 1200 nF/cm(2), showing an improvement on the gate efficiency and on state transconductance of over 100 times when compared with that of its back-gate counterpart.

A high-performance top-gate graphene field-effect transistor based frequency doubler

A high-performance top-gate graphene field-effect transistor (G-FET) is fabricated, and used for constructing a high efficient frequency doubler. Taking the advantages of the high gate efficiency and low parasitic capacitance of the top-gate device geometry, the gain of the graphene frequency doubler is increased about ten times compared to that of the back-gate G-FET based device. The frequency response of the frequency doubler is also pushed from 10 kHz for a back-gate device to 200 kHz, at which most of the output power is concentrated at the doubled fundamental frequency of 400 kHz.