Top-down Placement Research Articles

Multilevel optimization for large-scale hierarchical FPGA placement

This paper proposes a multilevel placer targeted at hierarchical FPGA (Field Programmable Gate Array) devices. The placer is based on multilevel optimization method which combines the multilevel bottom-up clustering process and top-down placement process into a V-cycle. It provides superior wirelength results over a known heuristic high-quality placement tool on a set of large circuits, when restricted to a short run time. For example, it can generate a placement result for a circuit with 5000 4-LUTs (4-Input Look Up Tables) in 70 seconds, almost 30% decrease of wirelength compared with than the heuristic implementation that takes over 500 seconds. We have verified our algorithm yields good quality-time tradeoff results as a low-temperature simulated annealing refinement process can only improve the result by an average of 1.11% at the cost of over 25-fold runtime.

Development of an Autonomous Biological Cell Manipulator With Single-Cell Electroporation and Visual Servoing Capabilities

Studies of single cells via microscopy and microinjection are a key component in research on gene functions, cancer, stem cells, and reproductive technology. As biomedical experiments become more complex, there is an urgent need to use robotic systems to improve cell manipulation and microinjection processes. Automation of these tasks using machine vision and visual servoing creates significant benefits for biomedical laboratories, including repeatability of experiments, higher throughput, and improved cell viability. This paper presents the development of a new 5-DOF robotic manipulator, designed for manipulating and microinjecting single cells. This biological cell manipulator (BCM) is capable of autonomous scanning of a cell culture followed by autonomous injection of cells using single-cell electroporation (SCE). SCE does not require piercing the cell membrane, thereby keeping the cell membrane fully intact. The BCM features high-precision 3-DOF translational and 2-DOF rotational motion, and a second z-axis allowing top-down placement of a micropipette tip onto the cell membrane for SCE. As a technical demonstration, the autonomous visual servoing and microinjection capabilities of the single-cell manipulator are experimentally shown using sea urchin eggs.

Hierarchical whitespace allocation in top-down placement

Increased transistor density in modern commercial ICs typically originates in new manufacturing and defect prevention technologies. Additionally, better utilization of such low-level transistor density may result from improved software that makes fewer assumptions about physical layout in order to reliably automate the design process. In particular, recent layouts tend to have large amounts of whitespace, which is not handled properly by older tools. We observe that a major computational difficulty arises in partitioning-driven top-down placement when regions of a chip lack whitespace. This tightens balance constraints for min-cut partitioning and hampers move-based local-search heuristics such as Fiduccia-Mattheyses. However, the local lack of whitespace is often caused by very unbalanced distribution of whitespace during previous partitioning, and this concern is emphasized in chips with large overall whitespace. This paper focuses on accurate computation of tolerances to ensure smooth operation of common move-based iterative partitioners, while avoiding cell overlaps. We propose a mathematical model of hierarchical whitespace allocation in placement, which results in a simple computation of partitioning tolerance purely from relative whitespace in the block and the number of rows in the block. Partitioning tolerance slowly increases as the placer descends to lower levels, and relative whitespace in all blocks is limited from below (unless partitioners return "illegal" solutions), thus preventing cell overlaps. This facilitates good use of whitespace when it is scarce and prevents very dense regions when large amounts of whitespace are available. Our approach improves the use of the available whitespace during global placement, thus leading to smaller whitespace requirements. Existing techniques, particularly those based on simulated annealing, can be applied after global placement to bias whitespace with respect to particular concerns, such as routing congestion, heat dissipation, crosstalk noise and DSM yield improvement.

Effective free space management for cut-based placement via analytical constraint generation

IP blocks and large macro cells are becoming more prevalent in the physical layout of a design, actually causing an increase in the available free space. We observe that top-down placement based on recursive bisection with multilevel partitioning performs poorly on these porous designs since it lacks a global view of the ideal placement. However, the strength of analytic placement methods lies in their ability to ascertain this global view. Consequently, we propose an enhancement to cut-based placement called analytic constraint generation (ACG). ACG utilizes an analytic engine to distribute available free space appropriately by determining balance constraints for each partitioning step. For one-dimensional placements, our experiments illustrate the large gap between analytic engines, traditional cut-based placement, and ACG as a design becomes increasingly sparse. We also show that for real industry designs, ACG significantly improves the performance of cut-based placement, particularly timing perspective, as implemented within a state-of-the-art industrial placer.

Routability-driven white space allocation for fixed-die standard-cell placement

The use of white space in fixed-die standard-cell placement is an effective way to improve routability. In this paper, we present a white space allocation approach that dynamically assigns white space according to the congestion distribution of the placement. In the top-down placement flow, white space is assigned to congested regions using smooth allocating functions. A post-allocation optimization step is taken to further improve placement quality. Experimental results show that the proposed allocation approach, combined with a multilevel placement flow, significantly improves placement routability and layout quality. A set of approaches for white space allocation has been presented and compared in this paper. All of them are based on routability-driven methods. However, these approaches vary in the allocation function and allocation aggressiveness. All the placement results are investigated by feeding them into a widely used industrial router (Warp Route of Cadence). Comparisons have been made between: 1) placement with or without white space allocation; 2) different white space allocation approaches; and 3) our placement flow, industrial placement tool, and the other state-of-the-art academic placement tool.

Congestion estimation during top-down placement

Congestion is one of the fundamental issues in very large scale integration physical design. In this paper, we propose two congestion-estimation approaches for early placement stages. First, we theoretically analyze the peak-congestion value of the design and experimentally validate the estimation approach. Second, we estimate regional congestion at the early stages of top-down placement. This is done by combining the wire-length distribution model and interregion wire estimation. Both approaches are based on the well-known Rent's rule, which is previously used for wirelength estimation. This is the first attempt to predict congestion using Rent's rule. The estimation results are compared with the layout after placement and global routing. Experiments on large industry circuits show that the early congestion estimation based on Rent's rule is a promising approach.

Hypergraph partitioning with fixed vertices [VLSI CAD

We empirically assess the implications of fixed terminals for hypergraph partitioning heuristics. Our experimental testbed incorporates a leading-edge multilevel hypergraph partitioner and IBM-internal circuits that have recently been released as part of the ISPD-98 Benchmark Suite. We find that the presence of fixed terminals can make a partitioning instance considerably easier (possibly to the point of being trivial); much less effort is needed to stably reach solution qualities that are near best-achievable. Toward development of partitioning heuristics specific to the fixed-terminals regime, we study the pass statistics of flat FM-based partitioning heuristics. Our data suggest that more fixed terminals implies that the improvements within a pass will more likely occur near the beginning of the pass. Restricting the length of passes-which degrades solution quality in the classic (free-hypergraph) context-is relatively safe for the fixed-terminals regime and considerably reduces the run times of our FM-based heuristic implementations. The distinct nature of partitioning in the fixed-terminals regime has deep implications: (1) for the design and use of partitioners in top-down placement; (2) for the context in which VLSI hypergraph partitioning research is pursued; and (3) for the development of new benchmark instances for the research community.

On wirelength estimations for row-based placement

Wirelength estimation in very large scale integration layout is fundamental to any predetailed routing estimate of timing or routability. In this paper, we develop efficient wirelength estimation techniques appropriate for wirelength estimation during top-down floorplanning and placement of cell-based designs. Our methods give accurate, linear-time approaches, typically with sublinear time complexity for dynamic updating of estimates (e.g., for annealing placement). Our techniques offer advantages not only for early on-line wirelength estimation during top-down placement, but also for a posteriori estimation of routed wirelength given a final placement. In developing these new estimators, we have made several contributions, including (1) insight into the contrast between region-based and bounding box-based rectilinear Steiner minimal tree (RStMT) estimation techniques; (2) empirical assessment of the correlations between pin placements of a multipin net that is contained in a block; and (3) new wirelength estimates that are functions of a block's complexity (number of cell instances) and aspect ratio.

Analytical Engines are Unnecessary in Top-down Partitioning-based Placement

The top-down “quadratic placement” methodology is rooted in such works as [36, 9, 32] and is reputedly the basis of commercial and in-house VLSI placement tools. This methodology iterates between two basic steps: solving sparse systems of linear equations to achieve a continuous placement solution, and “legalization” of the placement by transportation or partitioning. Our work, which extends [5], studies implementation choices and underlying motivations for the quadratic placement methodology. We first recall some observations from [5], e.g., that (i) Krylov subspace engines for solving sparse linear systems are more effective than traditional successive over-relaxation (SOR) engines [33] and (ii) that correlation convergence criteria can maintain solution quality while using substantially fewer solver iterations. The focus of our investigation is the coupling of numerical solvers to iterative partitioners that is a hallmark of the quadratic placement methodology. We provide evidence that this coupling may have historically been motivated by the pre-1990’s weakness of min-cut partitioners, i.e., numerical engines were needed to provide helpful hints to weak min-cut partitioners. In particular, we show that a modern multilevel FM implementation [2] derives no benefit from such coupling. We also show that most insights obtained from study of individual min-cut partitioning instances (within the top-down placement) also hold within the overall context of a complete top-down placer implementation.