Multilevel optimization for large-scale hierarchical FPGA placement

Abstract

This paper proposes a multilevel placer targeted at hierarchical FPGA (Field Programmable Gate Array) devices. The placer is based on multilevel optimization method which combines the multilevel bottom-up clustering process and top-down placement process into a V-cycle. It provides superior wirelength results over a known heuristic high-quality placement tool on a set of large circuits, when restricted to a short run time. For example, it can generate a placement result for a circuit with 5000 4-LUTs (4-Input Look Up Tables) in 70 seconds, almost 30% decrease of wirelength compared with than the heuristic implementation that takes over 500 seconds. We have verified our algorithm yields good quality-time tradeoff results as a low-temperature simulated annealing refinement process can only improve the result by an average of 1.11% at the cost of over 25-fold runtime.