Top-contact Thin-film Transistors Research Articles

Performance Analysis of Top Gate Top Contact TFT Using Different Dielectric Layers

Thin film transistors (TFT) have been gaining special attention from researchers in recent years because they are seen as an alternative to traditional MOSFET for future electronic device development. In this manuscript, the performance characteristics of n-channel Indium-Galium-Zinc-Oxide (IGZO) Top Gate Top Contact (TGTC) Thin Film Transistors (TFTs) for various insulating materials including Al2O3, Ta2O5, HfO2, Si3N4, SiO2, and Y2O3 are investigated and compared. This is followed by a comparison of p-type pentacene-based TGTC Organic Thin Film Transistors (OTFT). During simulation tests, the Silvaco Atlas tool is employed, and the I-V characteristic curve is analyzed to discover the important parameters. The proposed TFT's competency is demonstrated by extensive simulation results that contrast it with other models of a similar nature concerning threshold voltage, current ratio, subthreshold slope, mobility and Figure of Merit (FoM). The results demonstrate a trade-off between mobility and current ratio concerning the permittivity of the dielectric layer, with tantalum oxide (Ta2O5) providing the best outcomes in terms of FoM. According to simulation testing, the tantalum pentoxide (Ta2O5) gate insulating layer based on IGZO surpasses its rivals including the p-channel pentacene-based OTFT by offering mobility of 1.47 cm2V-1s-1, a current ratio of 1.36×106 and FoM of 198.87.

43.2: Parasitic Capacitance Model for BGTC TFTs and Verification Using C‐V Measurements from Devices with Various Channel Dimensions

A model of the accumulation and depletion capacitance for a bottom gate top contact (BGTC) thin film transistors (TFT) with an etch stop layer (ESL) was presented. The model, which includes the parasitic capacitance due to device layout, was verified by comparison of measured data and modeled data for TFTs of various dimensions. Good agreement was seen between measured and modeled data, where the model underestimated the capacitance by 2% to 7%, depending on the device dimensions. The impact of the parasitic capacitance on estimates of the Debye length (λD ) are discussed and it is demonstrated that the relative error in the λD estimates is directly proportional to the ratio of the parasitic capacitance over the measured capacitance (CPAR/CM). The relative error was shown to increase as the ratio increases, leading to a larger underestimation of the λD. It was concluded that the parasitic capacitance to measured capacitance should be minimized for devices that are used for extraction of physical parameters from C‐V data. This is especially important in the case where the λD is a critical parameter in the optimization of TFT performance.

Robustness of Passivated ALD Zinc Tin Oxide TFTs to Aging and Bias Stress

Thin-film electronics fabricated with amorphous oxide semiconductors (AOS) are being studied for beyond-display technologies because of their superior electron transport. To widen the commercial applications, robust devices fabricated using scalable deposition techniques are required. Here, we fabricate bottom-gate, top contact thin-film transistors (TFTs) using zinc tin oxide, an AOS deposited by atomic layer deposition (ALD), and study robustness to aging and bias stress for devices stored in a dark air ambient with and without Al2O3 passivation. All samples exhibit excellent mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {FE}}$ </tex-math></inline-formula> ) and subthreshold swing (SS) robustness to aging. Most of the device aging occurs within the first 25 days, after which the performance stabilizes. Changes due to positive bias stress, which are dominated by interactions with ambient molecules, are greatly reduced by passivation. Passivation, however, results in an increase in contact resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{C}$ </tex-math></inline-formula> ), SS, and negative bias illumination stress (NBIS) instability. The increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{C}$ </tex-math></inline-formula> is attributed to the diffusion of oxygen vacancies that occurs during the passivation process, while the increase in SS and NBIS instability is attributed to subgap interface defects. The experimental results are compared to Silvaco ATLAS simulations to confirm the proposed physical mechanisms and allow quantification of the associated defects and non-idealities.

High-performance polymer top-contact thin-film transistor with orthogonal photolithographic process

Based on fluorinated photoresist, an orthogonal lift-off process was introduced to directly fabricate patterning metallic source and drain contacts on polymeric thin films to obtain the top-contact structure device. Top-contact polymeric thin-film transistors (TFTs) on the wafer using this orthogonal lift-off process exhibited excellent value of electrical characteristics which was as high as 2.56 cm2V−1s−1 in mobility and >107 in on/off ratio. Compared with Ref. device which was fabricated by shadow mask, this top-contact polymeric TFTs showed the same mobilities but smaller channel length, and the lower contact resistance. In addition, based on fluorinated photoresist, the top-contact polymeric TFTs backplane with photo-patternable expoxy gate insulating layer was also successfully fabricated on glass. The mobility values of this OTFTs with different channel lengths ranged from 0.25 to 0.74 cm2V−1s−1 with an average of 0.48 ± 0.15 cm2V−1s−1 which can be comparable to the Ref. device with epoxy gate insulator using shadow mask method. It was further proved that the availability of such orthogonal photoresists promised to enable the fabrication of high performance OTFT device based the copolymer with long linear alkyl chains.

Performance Improvement in single-gate organic transistors with contacts at top and bottom: Additional p + region insertion near source and drain

This research explores performance attributes of bottom gate top contact (BGTC) and bottom gate bottom contact (BGBC) organic thin film transistors (OTFT). To upgrade the performance characteristics, a region of 5nm with high concentration of carrier is tallied neighboring contacts. The drain current for BGTC is –18.6μA as compared to –5.1μA of BGBC transistor. Also, it is established that the innate attributes of BGTC are better than those of their counterparts, which is typically considered because of the inadequate contact attributes and mediocre semiconductor quality of BGBC OTFT. The analysis showed that upon varying the length of the channel ranging from 5μm to 40μm, there was a significant change in the drain current of BGTC and BGBC devices. For the same values of VGS and VDS (0V to –5V) where drain current in BGTC structure varied from –129.86μA to –13.69μA, whereas for their counterparts it ranged from –37.10μA to –3.76μA for channel length equal to 5μm and 40μm respectively. Also, with the varying doping strength ranging from 1012 cm–3 to 1016 cm–3 for BGBC device, drain current varied from –2.15μA to –18.52μA for BGTC whereas for BGBC it varied from –0.19μA to –7.09μA keeping VGS and VDS –5 V, yielding that upon varying the doping strength, where for BGTC ID changed by a factor of 8.6, the BGBC device showed a considerable change by a factor of 37.3. Likewise, mobility, threshold voltage, sub-threshold swing and transconductance also showing better performance with the P + insertion. These variations in the innate attributes are primarily due to the deficiency of carriers at the interface of source and channel, leading to a greater drop in the potential, which is more prominent for the bottom gate bottom contact devices.

Different Materials, Structures and Parameters for Organic Thin Film Transistors

This paper assesses the topical progressions in the province of organic electronics especially the ones having SM and are made of polymer materials. It shows the analysis of structural disparity between top contact and bottom contact Organic Thin Film Transistors, thus rendering clarity to the conduction mechanism and performance governing parameters. Furthermore, an insight to a variety of materials that can be deployed in making different layers of an OTFT has been presented. In addition to this the parameters that oversee the performance of the device have also been highlighted. An elucidation of a variety of applications, limitations and scope has been reflected in the paper as well.

Large-Dimensional Organic Semiconductor Crystals with Poly(butyl acrylate) Polymer for Solution-Processed Organic Thin Film Transistors

Despite solution processed organic semiconductors have attracted much research attention, the randomized crystallization and large prevalence of grain boundary remain as a challenge to realize high performance organic electronic applications. In this work, we report the incorporation of poly(butyl acrylate) polymer additive with organic semiconductors with the mediation of a solvent vapor annealing method in order to modify the nucleation and crystal growth process. As 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) was experimented as a benchmark semiconductor, we demonstrated that the TIPS pentacene/poly(butyl acrylate) mixture exhibits rigidly aligned crystals, large grain width and improved areal coverage. In particular, thin film morphological characterization indicated a substantial reduction in misorientation angle by approximately two orders of magnitude as well as a 5-fold enlargement of grain width. A grain boundary model is proposed as a theoretic basis to understand the connection between grain width and hole mobility. Bottom-gate, top-contact thin film transistors based on TIPS pentacene/poly(butyl acrylate) blends demonstrated enhanced hole mobility of up to 0.11 cm2/Vs.

Extraction of source resistance in thin film transistors using a single gated-probe outside the channel

Extraction of source resistance in top contact thin film transistors (TFTs) is described using a gated three probe device structure. The three probes include a source terminal, a drain terminal and an electrode deposited outside the channel and kept open-circuited leading to unperturbed transistor operation. A measurement of floating potential of this probe together with a family of universal curves is presented, which allows estimation of source resistance from dc measurements in the linear mode of operation on a single device. Simulation results obtained for TFTs with different semiconductor technologies, like organic semiconductor pentacene, indium-gallium-zinc-oxide and amorphous silicon demonstrate the applicability of this technique. Experimental results obtained from organic TFTs with pentacene semiconductor confirm that the method gives estimates that are close to the values obtained from the relatively more complex transfer length measurement (TLM) technique. It is also shown that unlike the TLM method, the outside gated probe technique is much less sensitive to errors in device parameters and variations in device dimensions, such as the channel length.

Molecule Charge Transfer Doping for p‐Channel Solution‐Processed Copper Oxide Transistors

AbstractThe doping of semiconductors plays a critical role in improving the performance of modern electronic devices by precisely controlling the charge carrier density. However, the absence of a stable doping method for p‐type oxide semiconductors has severely restricted the development of metal oxide‐based transparent p–n junctions and complementary circuits. Here, an efficient and stable doping process for p‐type oxide semiconductors by using molecule charge transfer doping with tetrafluoro‐tetracyanoquinodimethane (F4TCNQ) is reported. The selections of a suitable dopant and geometry play a crucial role in the charge‐transfer doping effect. The insertion of a F4TCNQ thin dopant film (2–7 nm) between a Au source‐drain electrode and solution‐processed p‐type copper oxide (CuxO) film in bottom‐gate top‐contact thin‐film transistors (TFTs) provides a mobility enhancement of over 20‐fold with the desired threshold voltage adjustment. By combining doped p‐type CuxO and n‐type indium gallium zinc oxide TFTs, a solution‐processed transparent complementary metal‐oxide semiconductor inverter is demonstrated with a high gain voltage of 50. This novel p‐doping method is expected to accelerate the development of high‐performance and reliable p‐channel oxide transistors and has the potential for widespread applications.

Reliable inkjet contact metallization on printed polymer semiconductors for fabricating staggered TFTs

Even though the fundamental benefits of the staggered bottom-gate top-contact geometry in organic thin-film transistors (TFTs) have been fully demonstrated for enhancing the charge injection efficiency, most printed organic TFTs with inkjet-printed source/drain electrodes have only been fabricated in bottom-contact configurations, probably due to the difficulty of printing with metal-nanoparticle ink on soluble organic semiconductor (OSC) without film deformation/dissolution. Here, we present the printing process and the electrical characteristics of inkjet-printed top contact OSC in bottom-gate TFTs. We first fabricated polymer bottom-gate TFTs by printing in two different top- and bottom-contact configurations. The physical carrier mobility of the two TFTs was extracted from a gated-contact organic TFT model to exclude the effect of geometric contact resistance RC. When compared to assess the OSC film damage from the printing metallization, the two mobility values were almost identical. This result indicates that the metal nanoparticle ink used in this work formed a top metal contact on the OSC film without significant chemical damage. Furthermore, the printed top-contact TFT exhibited I–V characteristics almost identical to those of a thermally evaporated Ag top-contact TFT. This study suggests the possibility of inkjet-printed top metal contacts for organic thin-film devices such as transistors, solar cells, and diodes.

Solution-Processed Amorphous Zinc Oxide Thin Film Transistor Based NAND Gate

Herein, we discuss the synthesis and deposition of thin films amorphous zinc oxide (a: ZnO) by custom-designed spray pyrolysis unit for Thin Film Transistor (TFT) application towards NAND gate fabrication. Top gate top contact TFT was fabricated on a glass substrate, a: ZnO as the channel layer, PVA as gate dielectrics material and Al as electrodes. Electrical properties of a: ZnO TFT (W/L = 500/200μm) were probed. The individual transistor with a threshold voltage (Vth = 2.1 V), off and on current (Ioff = order of 10-8A; Ion = 10-3) and Ion / Ioff ratio (order of 105). The linear mobility is calculated and obtained as 3 cm-2/Vs. NAND gate is one of the universal and basic building blocks of a digital circuit. The fabricated NAND gate is subjected to the logic operation in the range of 0 to 10 V was tested. The result implies that it can be utilized for logical circuit operation.

Solution-processed Pb0.8Ba0.2ZrO3 as a gate dielectric for low-voltage metal-oxide thin-film transistor

A solution-processed low-voltage metal-oxide thin-film transistor (TFT) is fabricated by using ferroelectric perovskite structure barium zirconate (PBZ) as gate dielectric. This PBZ thin film is deposited on heavily doped Si substrate (p++-Si) by low-cost sol-gel process followed by annealing at 830 °C. The thin film is characterized by XRD, UV-Vis absorption spectroscopy and atomic force microscopy (AFM) that reveals fully oxidized PBZ thin film is highly crystalline in nature with high optical transparency in visible region that exhibited a lower roughness of 4.6 nm. Solution-processed indium zinc oxide (IZO) has been used as a channel semiconductor for bottom-gate top-contact TFT. The fabricated device require < 5 V operating voltage to saturate with high drain current which is very beneficial for low-power electronics because of its low operating voltage with respect to convention SiO2 gate dielectric device that required ~ 40 V operating voltage. This typical TFT shows an excellent electron mobility of 4.5 cm2 V−1 s−1 with on/off ratio 5 × 103 and subthreshold swing 0.35 V/decade.

Thin film transistor based on two-dimensional organic-inorganic hybrid perovskite

Despite the fact that three-dimensional organic-inorganic hybrid perovskite is regarded as a promising material in the field of optoelectronics and microelectronics due to its excellent photoelectric properties, however, the instability under the moisture environment and the gate-voltage screening effect associated with ionic transport are still serious, which restricts the development of perovskite devices. Here in this work, the lead iodide perovskite (PEA)&lt;sub&gt;2&lt;/sub&gt;(MA)&lt;i&gt;&lt;sub&gt;n–&lt;/sub&gt;&lt;/i&gt;&lt;sub&gt;1&lt;/sub&gt;Pb&lt;sub&gt;n&lt;/sub&gt;I&lt;sub&gt;3&lt;i&gt;n&lt;/i&gt;+1&lt;/sub&gt; series are successfully prepared by one-step solution method, including pure-two-dimensional (pure-2D), quasi-two-dimensional (quasi-2D) and traditional three-dimensional (3D) perovskite materials. The dimension and microstructure of the perovskites are regulated, and the effects of dimensions on the performance of organic-inorganic hybrid perovskite materials are investigated firstly. The crystallization of the 2D perovskites and 3D perovskite films are observed obviously. Moreover, the surface of pure-2D perovskite film with discoid, regular and micron-sized grains is smoother than that of 3D perovskite film. And also, the unapparent grain boundary is exhibited in the quasi-2D perovskites. A uniform perovskite film with full coverage and inconspicuous grain boundaries facilitates the transmission capacity of the charge carriers in the channel layer due to the reduction of defects caused by the grain boundaries. And benefited from the high-quality films with inconspicuous grain boundary as demonstrated, the quasi-2D hybrid perovskite film exhibits a longer carrier lifetime (&lt;i&gt;τ&lt;/i&gt;&lt;sub&gt;ns&lt;/sub&gt;) than traditional 3D MAPbI&lt;sub&gt;3&lt;/sub&gt; perovskite film, revealing that the layered 2D structure is more favorable for carrier transport due to the fewer defects in it. In addition, under the condition of the same environment humidity, the 2D perovskite materials show better moisture stability. Then, to investigate the influences of dimensional structure on the perovskite field-effect devices, we fabricate the bottom-gate and top-contact thin film transistors (TFTs) based on the perovskite materials with different dimensions. As a result, the instability and ion migration effect for each of the devices are suppressed effectively due to the distinct 2D layer-structure and quantum confinement effect, which leads the device performance to be further improved. The device based on quasi-2D (&lt;i&gt;n&lt;/i&gt; = 6) channel TFT achieves a hole mobility (&lt;i&gt;μ&lt;/i&gt;&lt;sub&gt;hole&lt;/sub&gt;) of 3.9 cm&lt;sup&gt;2&lt;/sup&gt;/(V·s), an on-off current ratio of 10&lt;sup&gt;4&lt;/sup&gt; and more, and a 1.85V turn-on voltage of 1.85 V. The first application of quasi-2D organic and inorganic hybrid perovskite materials to thin film transistors provides a new idea for preparing the high-performance and stable thin film transistor devices.

Fabrication of high-performance solution processed thin film transistors by introducing a buffer layer

In this paper, high quality ZrO2 and In2O3 films were prepared by solution method. Based on the solution-processed ZrO2 dielectric and In2O3 semiconductor layer, bottom-gate top-contact thin-film transistors (TFTs) were integrated. XPS depth profile was carried out to investigate the intersecting region between ZrO2 insulator and In2O3 active layer due to the diffusion of the subsequent precursor solution, and the effect of intersecting region on the electrical performance of TFTs was discussed. In order to narrow the intersecting region, a simple way that introducing a buffer layer between the active layer and the insulating layer was proposed. The effect of buffer layer was investigated by the multifactor analysis on Minitab software and the result indicated that the buffer layer can effectively improve the performance of TFTs. Finally, high-performance solution processed Thin Film Transistor was fabricated with 0.05 M buffer layer solution and 0.10 M active layer solution. Compared with the TFT without buffer layer, the mobility of TFT with buffer layer increased from 4.35 to 43.94 cm2/Vs, and the Ion/Ioff increased from 1.87 × 105 to 3.90 × 106.

Passivation of Thin Channel Zinc Tin Oxide TFTs Using Al2O3 Deposited by O3-Based Atomic Layer Deposition

Here, we fabricate solution processed zinc tin oxide bottom gate top contact thin film transistors (TFTs) with active layer thickness down to 6 nm by varying the solution molarity and number of layers. As-fabricated devices show hysteresis as large as 12.65 V. The hysteresis is then studied under vacuum to understand the important role of the back channel in electrical performance. After vacuum treatment, the hysteresis measured under vacuum was reduced to −0.05 V. Alumina deposited on the back channel using atomic layer deposition (ALD) is used for passivation. The TFTs passivated with an H2O-based ALD process show conductive behavior after passivation while an O3-based ALD process results in a negative threshold voltage shift dependent on the thickness of the active layer. O3-based passivated devices show good stability with a field effect mobility of 8.3 cm2V−1s−1, ${V}_{t}$ of 5.5 V, and hysteresis of 0.85 V.

High mobility solution processed MoS2 thin film transistors

A simple wet-chemical synthesis of layered MoS2 thin films on sapphire is reported. The gap in understanding solution processed MoS2 deposition needs to be closed to exploit all its excellent properties for low-cost applications. In this work, as deposited Mo-precursor thin films were prepared based on the solubility and coating properties of Molybdenum(V) chloride in 1-Methoxy-2-propanol. Subsequent annealing of the deposited amorphous Mo-precursor films in the presence of sulfur resulted in the formation of highly crystalline layered MoS2 films on sapphire. Improved crystallinity of the deposited films was achieved by increasing the process temperature and performing the post-annealing treatment. Post-annealing at temperatures above 900 °C increased the uniformity of multilayer films, together with the increase of MoS2 grain size. For charge transport analysis, top-gate top-contact thin film transistors (TFTs) based on these solution processed MoS2 films were fabricated. Ionic liquid gating of the TFT devices exhibited n-type semiconducting behaviour with field-effect mobility as high as 12.07 cm2/Vs and Ion/off ratio ∼ 106. X-ray photoelectron spectroscopy measurements revealed that the films annealed between 900 °C and 980 °C had an average chemical composition of S/Mo ∼ 1.84. This facile liquid phase synthesis method with centimeter-scale uniformity and controllable film thickness up to 1.2 ± 0.65 nm is suitable for low-cost preparation of other transition metal dichalcogenides thin films in next-generation electronics.

Small contact resistance and high-frequency operation of flexible low-voltage inverted coplanar organic transistors

The contact resistance in organic thin-film transistors (TFTs) is the limiting factor in the development of high-frequency organic TFTs. In devices fabricated in the inverted (bottom-gate) device architecture, staggered (top-contact) organic TFTs have usually shown or are predicted to show lower contact resistance than coplanar (bottom-contact) organic TFTs. However, through comparison of organic TFTs with different gate-dielectric thicknesses based on the small-molecule organic semiconductor 2,9-diphenyl-dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene, we show the potential for bottom-contact TFTs to have lower contact resistance than top-contact TFTs, provided the gate dielectric is sufficiently thin and an interface layer such as pentafluorobenzenethiol is used to treat the surface of the source and drain contacts. We demonstrate bottom-contact TFTs fabricated on flexible plastic substrates with record-low contact resistance (29 Ωcm), record subthreshold swing (62 mV/decade), and signal-propagation delays in 11-stage unipolar ring oscillators as short as 138 ns per stage, all at operating voltages of about 3 V.

Evaluation of the Beyond-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$f_T$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Operation of an IGZO TFT-Based RF Self-Mixing Circuit

The objective of this letter is to show the potential of amorphous indium gallium zinc oxide (IGZO) thin-film transistors (TFT) for designing radio frequency (RF) communication systems operating in the gigahertz regime. For that purpose, the self-mixing operation of in-house fabricated IGZO-TFTs beyond their transit frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) is reported. The bottom-gate, top-contact TFTs have an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 40 MHz including the device interconnects. A differential RF self-mixing circuit was fabricated to act as an RF detector and frequency doubler. The detector shows a peak voltage responsivity (RV) and a minimum noise equivalent power of 445 V/W and 0.1 nW/√(Hz) at 50 MHz and 2 V/W and 30 nW/√(Hz) at 1 GHz, respectively, at a chopping frequency of 28 kHz. As a frequency doubler, the circuit can generate a second-harmonic output voltage up to -36 dBV for an 8-dBV RF input voltage at 100 MHz.

Double active layer InZnO:N/InZnSnO thin film transistors with high mobility at low annealing temperature

In this paper, bottom-gate top-contact thin film transistors (TFTs) with a double active layer of InZnO:N/InZnSnO (IZO:N/IZTO) were successfully prepared. The IZO:N/IZTO thin films were deposited on SiO2/p-Si substrates by radio frequency (RF) magnetron sputtering at room temperature. The transmittance of both the IZO:N thin film and the IZTO thin film were more than 80% in the range of visible light. The IZO:N thin film and the IZTO thin film were found to be amorphous at the annealing temperature of 325 °C by means of X-ray diffraction (XRD). The double active layer IZO:N/IZTO TFT exhibited good electrical performance with a saturation mobility of 41.5 cm2 V−1 s−1, an on/off current ratio of 2.88 × 105, and a threshold voltage of 1.0 V, which achieved high mobility at the low annealing temperature of 325 °C.

Solution processed low band gap ion-conducting gate dielectric for low voltage metal oxide transistor

Low band gap ion conducting Li2ZnO2 thin film has been synthesized by low cost solution processed technique and has been employed to fabricate low operating voltage metal oxide thin film transistor (TFT) with high device performance. Li2ZnO2 is a known ion conducting oxide material, generally used as solid state electrolyte in different applications including fuel cell and Li ion battery. Instead of having low band gap, Li2ZnO2 thin film shows very insulating behavior and low leakage current. Additionally, it shows high dielectric constant (κ) that originated from the conducting nature of its Li+ ion, serve as a gate dielectric for low operating voltage metal oxide TFT. In addition to this dielectric, tin oxide (SnO2) semiconductor channel has also been deposited in solution processed technique in the bottom gate top contact TFT structure. Such kind of TFT device requires only 2.0 V or less drain voltage with the gate bias in the range of 2.0-V to saturate the drain current. The extracted carrier mobility, on/off ratio and subthreshold voltage for Li2ZnO2 based TFT are 23 cm2 V−1 s−1, 6 × 103 and 390 mV dec−1 respectively. The device parameters have been compared with sol-gel derived reference Li2O dielectric, which clearly indicates the superiority of Li2ZnO2 dielectric in the performance of TFT.