Extraction of source resistance in thin film transistors using a single gated-probe outside the channel

Abstract

Extraction of source resistance in top contact thin film transistors (TFTs) is described using a gated three probe device structure. The three probes include a source terminal, a drain terminal and an electrode deposited outside the channel and kept open-circuited leading to unperturbed transistor operation. A measurement of floating potential of this probe together with a family of universal curves is presented, which allows estimation of source resistance from dc measurements in the linear mode of operation on a single device. Simulation results obtained for TFTs with different semiconductor technologies, like organic semiconductor pentacene, indium-gallium-zinc-oxide and amorphous silicon demonstrate the applicability of this technique. Experimental results obtained from organic TFTs with pentacene semiconductor confirm that the method gives estimates that are close to the values obtained from the relatively more complex transfer length measurement (TLM) technique. It is also shown that unlike the TLM method, the outside gated probe technique is much less sensitive to errors in device parameters and variations in device dimensions, such as the channel length.