Au Top Layer Research Articles

Alloyed and Non-Alloyed Ohmic Contacts for AlInAs/ InGaAs High Electron Mobility Transistors

AuGe/Ni/Au alloyed and WSi non-alloyed ohmic contacts are investigated for AlInAs/InGaAs high electron mobility transistors (HEMTs). For the alloyed contact, a contact resistance (R c) lower than 0.03 Ω mm is obtained at an alloy temperature of 300°C. The value of R c drastically increases with alloy temperatures above 300°C and exceeds 0.15 Ω mm at 380°C. Auger analysis and analytical cross-sectional transmission electron microscopy have revealed significant outdiffusion of In in the epitaxial layer into the top Au layer and the formation of polycrystalline GaAs in the epitaxial layer, which cause the increase of R c with alloy temperature. For the refractory WSi non-alloyed ohmic contact, R c remains lower than 0.1 Ω mm under annealing temperatures up to 380°C. The extrinsic maximum transconductance (g m) of 600 mS/mm is obtained for the HEMT device with the WSi ohmic contact.

Au(111): A theoretical study of the surface reconstruction and the surface electronic structure.

On the reconstructed Au(111) surface, atoms on the surface layer occupy both the hcp and the fcc sites. Using first-principles calculations to obtain the surface energies of the system with the top Au layer occupying the fcc, hcp, top, and bridge sites, we found that the hcp site is only 1 mRy per surface atom higher in energy than the fcc site. The complex Au(111) reconstruction is then discussed with use of a two-dimensional Frenkel-Kontorowa model. We calculated the surface band structure of the Au(111) surface along high-symmetry lines in the surface Brillouin zone, with the top layer occupying the fcc, hcp, and bridge sites. We found that the surface electronic structure is almost independent of the position of the top layer.

In-Based Ohmic Contacts to the Base Layer of GaAs-AlGaAs Heterojunction Bipolar Transistors

ABSTRACTThe use of AuBe-In/Ag/Au p-ohmic contacts for the base layer of GaAs-AIGaAs heterojunction bipolar transistors (HBTs) is described. Annealing at 420°C for 20 sec produces a contact resistivity of 0.095 Ω mm and a specific contact resistance of l.5 × 10-7 Ω cm2, and the surface morphology of the contact is excellent. The role of the silver is as a diffusion barrier to prevent Au spiking into the base layer which could degrade the HBT performance. The presence of the In layer is highly desirable in order to reduce the contact resistance, probably by forming an InGaAs phase at the metal-GaAs interface. Beryllium acts as the p-type dopant, and the top Au layer is used to lower the contact sheet resistance. Current transport through the structure is dominated by tunneling through the barrier due to field emission in the highly doped base layer at p-type doping levels above ∼1019 cm−3

Stable solid-phase contact to n-GaAs

An ohmic contact to n-type GaAs of the configuration GaAs/Ni/Ge/W/sub 60/N/sub 40//Au has been investigated. The contacting layer in this metallization is formed by a solid-state reaction between Ni/Ge and GaAs. Backscattering spectrometry and electrical measurements show that the interposed W-N layer acts as an excellent diffusion barrier both in preventing the intermixing of the top Au layer with Ni/Ge and in confining the reaction between Ni/Ge and GaAs. The contact resistivity is in the range of 10/sup -6/ Omega cm/sup 2/ and remains stable after annealing at 500 degrees C for 60 min. >

Au-Be/Au and Au-Be/Cr/Au ohmic contacts to p-type InP and InGaAsP

A comparison of vacuum-deposited Au-Be/Au and Au-Be/Cr/Au metallisations, used for the preparation of ohmic contacts to p-type InP and InGaAsP, is presented. The electrical and metallurgical properties of such contacts were studied as a function of material parameters and of deposition and alloying conditions. The alloying temperature and time were found to be the important factors that strongly influence the contact properties. As a result, ohmic contacts to p-type InP and 1.3 mu m in InGaAsP (with NA-ND approximately=1024 m-3) could be formed with the lowest values of specific contact resistance of about 3.5-4.5*10-8 Omega m2 and 2.5-3.0*10-9 Omega m2 respectively, at the optimum alloying conditions of 3 min at 420-430 degrees C. AES depth-composition profile measurements and SIMS surface analysis were used to study the thermally induced reactions at the metallisation-semiconductor interface accompanying the formation of ohmic contacts. The profiles obtained showed that a Cr layer incorporated between the thin Au-Be contact layer and a relatively thick Au top layer, acts as an effective barrier against the out-diffusion of phosphorus from the semiconductor and also against the migration of gold from the Au top layer into the semiconductor during the heat treatment of contacts.

Interface Failure of Gold Covered SiO2 Substrate With TiW and Nb Intermediate Adhesion Layers

AbstractIn this paper, we report an electron microscopy study (SEM and TEM) of the Au-TiW-SiO2 structure annealed in ambient air up to 600°C. Scanning Auger microscopy has also been used to characterize the interfaces. Growth of pyramid- like structures was found to occur under heat treatment above 450°C. Volume increase and adhesion failure due to oxidation of the TiW layer and weak points in the Au top layer were found to be at the origin of this particular growth. Similar surface failures have been reported under oxidation at higher temperature for the tungsten silicide – SiO2 systems. According to the assumed growth mechanism, the necessary conditions for a pyramid growth have been defined and checked on another multilayer structure, that is the Au-Nb-SiO2 interface.

Submicrometer gate fabrication of GaAs MESFET by plasma etching

Dry etching is employed in the direct fabrication of the main part of semiconductor devices. A submicrometer Schottky-barrier gate is constructed for GaAs MESFET's. The gate has a double-metal-layer configuration. The Au top metal layer is first delineated by ion milling with monitoring equipment, i.e., ion microanalyzer. The metal layer in contact with the GaAs substrate is chemically etched in CF <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> gas plasma. Controlled side etching of the Mo metal produces the submicrometer gate, leaving a wider top metal layer of Au. The amount of side etching deviates less than 0.05 µm and the gate length is reduced to 0.1 µm. No appreciable damage to the GaAs substrate is found as a result of plasma etching. Half-micrometer gate GaAs MESFET's fabricated by this dry etching technique achieved high-gain and low-noise performance in the X-band.