Token Ring Architecture Research Articles

Low Power QC-LDPC Decoder Based on Token Ring Architecture

The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

An Asynchronous Analog Self-Powered CMOS Sensor-Data-Logger With a 13.56 MHz RF Programming Interface

Design and implementation of a hybrid energy scavenging integrated circuit (IC) is presented which includes an asynchronous self-powered analog sensor-data-logger (SDL) unit and a 13.56 MHz radio-frequency (RF) programming interface. The SDL unit operates on an event-based analog self-powering technique where the energy for sensing, computation and non-volatile storage is harvested directly from the signal being sensed. By exploiting operational primitives inherent in a controlled hot-electron injection mechanism, the SDL unit eliminates the need for voltage regulation, energy storage, ADCs, MCUs and RAMs which are commonly used in traditional energy scavenging sensors. Remote programming and data interrogation of the SDL unit are performed using an integrated 13.56 MHz RF back-telemetry interface. The interface consists of a 6-instruction set digital command and control unit based on a token-ring architecture; a high-voltage generator for programming floating-gate (FG) transistors; and an RF front-end unit for communicating with an external reader. We show that the self-powered design is suitable for integration with electro-capacitive transducers (e.g., piezoelectric transducers) that can generate open-load voltages greater than 5 V and drive currents less than 200 nA. Measured results from prototypes fabricated in a 0.5-μ m standard CMOS process demonstrate that the IC consumes less than 90 nA in the self-powering mode and less than 200 μW of power in the RF-powering mode with an interrogation distance up to 40 mm. By combining self-powering and RF-powering, we show that the sensor experiences minimum down-time and can continuously monitor and record level-crossing statistics of different attributes of sensor signals.

Hardware Design of Wireless Physical Token Ring System for Mobile and Cellular Communication

A wireless network system based on an infrared and Laser scanning Physical Token Ring architecture (W-PTRS) was designed, built and tested successfully. The network provides a different way of utilizing the concept of a token ring network but with a higher efficiency related to the speed of data transfer and the ability to parallel process client-server requests leading to a new concept of the token ring system, which will not fail simply because of ring breakage. The study proposes a new wireless communication protocol, which is neither IEEE802.11 nor Bluetooth. This newly developed protocol could prove to be an excellent communication media if supported by industry. If implemented, this wireless system will provide an alternative but efficient way of wireless communication.

Local-area network reliability models

This paper describes analyses of reliabilities of local area networks (LANs) designed according to the most common IEEE 802 standards: the token ring architecture (IEEE 802.5, basically the IBM token ring architecture), carrier sense multiple access/collision detection (CSMA/CD) bus architecture (IEEE 802.3, basically the Ethernet architecture) and token bus architecture (IEEE 802.4, the recommended LAN architecture for the manufacturing atomation protocol, MAP). Each of these architectures is assumed to be implemented using electrical conductors; newer architectures using fibre optics (such as FDDI) are currently being studied. The primary reliability parameter studied is average source-destination availability. The models are based on information in the standards plus implementation details, using more implementation details than previous reliability models. Approximate analyses, which reflect all architecture details that appear to be pertinent to availability, have been developed, rather than exact analyses which ignore fine details. One conclusion is that details neglected in previous models have major effects on, and may be the most important factors determining, source–destination availability. At present, no measured values for the relevant parameters are obtainable, however, so all of our computations are based on arbitrary ‘guesstimates’ of these parameter values. A few other conclusions can be reached. Since major components of the bus networks (CSMA/CD and token bus) are similar, reliabilities of these networks are also similar, with differences determined primarily by differences in parameters. Adequate data to describe these differences were not obtainable, so our example computations for the two bus networks yield essentially the same results. Although its use of an active communications medium, instead of the passive bus used by the other architectures, may decrease reliability of the token ring, the token ring architecture gives more flexibility in bypassing or recovering from error situations. In some situations this could make the token ring the most reliable LAN, but ‘reasonable’ choices of parameter values could make any of the LANs most reliable. If many stations are inactive, however, any reliability advantage for token rings would be eliminated by even a small probability that inactive stations are not successfully bypassed

The IBM token-ring network — A functional overview

The IBM token-ring network, which is based on a ring topology with token-access control, is described. In particular, a star-wired ring topology and the functions of several of the key physical components that compromise a token-ring network are examined. The token-access control protocol for regulating data flow on the ring is explained, including the data frame format and addressing structures, mechanisms for ensuring token integrity and fair token access to all attached nodes, and some token-ring performance attributes. The relationship between the token-ring architecture and systems network architecture (SNA) is also discussed. Some of the fault detection and isolation capabilities that are available with the token-ring LAN are also presented.

IBM academic information systems (ACIS): The IBM-PC on the IBM token-ring network

Abstract With the availability of an IBM Token-Ring Network conforming to the European Computer Manufacturers Association (ECMA) standards 89, and to the Institute of Electrical and Electronics Engineers (IEEE) 802.5 a new base for communicating between Personal Computer (PC) has arisen. IBM has actively participated into the Star wiring, Token-Ring architecture development and has now a full range of products available from PC's to Main Computers. The applications of this architecture are numerous; amongst wish Scientific Environments. CERN Geneva is currently implementing a Token-Ring based PC to PC communication for their new Main Control Room which will be used to control both the future Large Electron Positron (LEP) collider ring and the existing Super Proton Synchrotron (SPS) accelerator. This article summarize the IBM products available and describes the CERN application. The development and implementation made at CERN where based on a CERN-IBM joint Study Agreement.