Today's High Performance Research Articles

Dual-crosslinking network and pre-anchorage effect enable high-performance, low-cost, and eco-friendly geopolymer adhesive for the wood industry

Alkali-activated geopolymers have shown unique advantages in applying adhesive materials because of their low cost, flame retardancy, and environmental friendliness. However, the high brittleness of the single aluminosilicate network and the weak interfacial compatibility of the geopolymer system result in poor bonding performance, which severely limits their application in the adhesives industry. Herein, a geopolymer-PF resin adhesive (GPA) with excellent comprehensive performance was successfully prepared by crosslinking geopolymer and PF resin with numerous reactive sites for the strong hybrid dual network under hot-pressing. In addition, the introduction of PF resin can achieve an effective pre-anchorage effect on wood for strong mechanical locking due to the excellent wettability, water resistance, and dimensional stability of PF resin. The produced GPA exhibits high initial wet shear strength (0.94 MPa) and adhesion toughness (0.271 J), 236% and 450% higher than pure geopolymer. The GPA also demonstrated remarkable age-strengthen performance, with bonding strength increasing to 1.27 MPa after 28 d, exceeding the majority of reported inorganic, biomass, and PF adhesives. In addition, the GPA displayed desirable eco-friendly and flame-retardant properties with a low-cost and sustainable approach. The pre-anchorage and double network structure design provide a general strategy for strengthening and toughening geopolymers, a key step forward in today's high-performance, low-cost, and sustainable production of inorganic adhesives from industrial solid wastes and geological resources.

Metapneumovirus infection in poultry

Today's high performance in the industrial poultry industry would not have been possible without the focused specialization of production and the use of highly productive poultry crosses. Therefore, the organization of modern poultry farming used simultaneously with high productivity indicators leads to a decrease in natural resistance and an increase in the susceptibility of birds to various pathogens of infectious diseases transmitted aerogenically, which is accompanied by the manifestation of respiratory syndrome in birds. One of the key reasons for the development of respiratory syndrome is the circulation of pneumovirus in the herd, which is especially dangerous for meat farms, since in broiler chickens the disease proceeds in a more severe form compared to poultry crosses.Avian metapneumovirus infection causes significant economic damage to poultry farming, which consists of losses from a decrease in safety and productivity, as well as the cost of health and preventive measures.4 subtypes of MPV are officially known, although recent publications have reported of two new pneumoviruses, GuMPV and AMPV PAR-05 isolated from the seagull in North America.The diversity of pathogen subtypes and differences in virulence properties of metapneumovirus create difficulties both in the prevention of this disease and in its diagnosis.Difficulty of metapneumovirus isolation from the examined material is caused by the short period of virus persistence in the organs of birds.The most effective method of controlling avian MPVI is vaccination.

State of the art and future prospective of high performance streak cameras for laser fusion

The streak cameras have very important applications in Inertial Confinement Fusion (ICF), including x-ray streak cameras and optical streak cameras. At present, they are still the core diagnostic devices with the highest temporal resolution in this field. This paper introduces the performance and characteristics of two main types of the streak cameras widely used in the field of laser fusion both domestic and international. They are equipped with coaxial electrode double-focus electron optics streak tube and bilamellar electron optics streak tube respectively. In terms of specifications of streak camera, the criteria of dynamic range of streak camera are emphasized, the dynamic range data of today's international high performance streak cameras are presented. The paper also introduces several important research progresses in the development of streak camera technologies, including advanced backlighting ultraviolet fiducial system, neutron radiation tolerant device and gated cathode technology.

Single / multi TCP and a fairness issue

In distributed systems domain a good connection is a structural quest for messages transfer between clusters in today's high performance applications. Initiating a single TCP used in networks, than it drops as a bundle of TCP's called multiple or parallel TCP. This drop wasn't quite successful it also created some ugly fouling , for this reason some studies concluded that in general resultant a multi TCP is not much differ of a single TCP ,but others refined that the multi socket TCP achieves better throughput and performance than the single socket approach [1]. The applications that require good network performance often use multi socket TCP streams and TCP modifications to improve the effectiveness of TCP .but if the network bottleneck is fully utilized, this approach boosts throughput by unfairly stealing bandwidth from competing TCP stream. This dilemma driven to some opinions see that improve the effectiveness of TCP is much easier than to while maintaining fairness [2]. in this paper we submit our own destination to compare between single-socket TCP and multi-socket TCP to conclusiveness the argumentativeness according about any one is the best, in performance and throughput ,we also discussed a fairness issue in both ,and finally we defined an algorithm for enhance multi TCP's performance.

Hierarchical Collective I/O Scheduling for High-Performance Computing

The non-contiguous access pattern of many scientific applications results in a large number of I/O requests, which can seriously limit the data-access performance. Collective I/O has been widely used to address this issue. However, the performance of collective I/O could be dramatically degraded in today's high-performance computing systems due to the increasing shuffle cost caused by highly concurrent data accesses. This situation tends to be even worse as many applications become more and more data intensive. Previous research has primarily focused on optimizing I/O access cost in collective I/O but largely ignored the shuffle cost involved. Previous works assume that the lowest average response time leads to the best QoS and performance, while that is not always true for collective requests when considering the additional shuffle cost. In this study, we propose a new hierarchical I/O scheduling (HIO) algorithm to address the increasing shuffle cost in collective I/O. The fundamental idea is to schedule applications' I/O requests based on a shuffle cost analysis to achieve the optimal overall performance, instead of achieving optimal I/O accesses only. The algorithm is currently evaluated with the MPICH3 and PVFS2. Both theoretical analysis and experimental tests show that the proposed hierarchical I/O scheduling has a potential in addressing the degraded performance issue of collective I/O with highly concurrent accesses.

Labor Codes and Human Resource Strategy in Emerging Economies

Labor codes have been voluntarily adopted and used by manufacturers across multiple industries for the past two decades or more, as means of ensuring minimally acceptable or core labor standards for workers. However, far too little is known of the potential benefits and consequences from the adoption of labor codes to the manufacturer, and prior strategic human resource management (SHRM) research has been virtually silent on their role in today's global high performance work organizations. Drawing on previous work across multiple disciplines, this study theorizes and demonstrates that the voluntary adoption of a labor code in an emerging economy context may constitute a human resource strategy that is just as effective, if not more effective than a high performance work system (HPWS) in improving establishment-level employee outcomes, and operational and financial performance. Hypotheses are tested using longitudinal data on a large sample of apparel manufacturing plants in Sri Lanka. Implications for SHRM include a need to expand the range of human resource strategies considered in research and practice with regards to firms and establishments, and subsidiaries of multinational companies located in emerging economies.

Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor

In nanometer technologies, local interconnects are believed to cause a major impact on timing and power in VLSI circuits. To assess the impact of the interconnects on timing and power in a real high performance microprocessor design in a quantitative manner, this article presents results from an extensive study carried out on RTL-to-layout synthesized blocks in a 45-nm technology core. The study shows that the interconnects in these blocks account for 30% of the cycle time, on an average, on the worst internal timing paths and contribute nearly one-third to the power dissipation. This points to severity of impact due to the interconnects in today's high performance designs.

Three-Dimensional Numerical Simulation of a 30-GHz Gyrotron Resonator With an Explicit High-Order Discontinuous-Galerkin-Based Parallel Particle-In-Cell Method

Fast design codes for the simulation of the particle–field interaction in the interior of gyrotron resonators are available. They procure their rapidity by making strong physical simplifications and approximations, which are not known to be valid for many variations of the geometry and the operating setup. For the first time, we apply a fully electromagnetic (EM) transient 3-D high-order discontinuous Galerkin particle-in-cell method solving the complete self-consistent nonlinear Vlasov–Maxwell equations to simulate a 30-GHz high-power millimeter-wave gyrotron resonator without physical reductions. This is a computational expensive endeavor, which requires today's high-performance computing capacity. However, this enables a detailed analysis of the EM field, the excited <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{TE}_{2, 3}$</tex></formula> mode, the frequencies, and the azimuthal particle bunching in the beam. Therefrom, we present new insights into the complex particle–field interaction of the electron cyclotron maser instability transferring kinetic energy from the electron beam to the EM field.

Creep and fatigue interaction in the PWA1484 single crystal nickel-base alloy

While methods for modeling creep behavior of single crystal turbine airfoils are generally well developed, constant load creep does not fully represent the loading conditions present in a jet engine due to cyclic loading caused by the mission profile and throttle movements. As the aerospace industry seeks to become more accurate in physics-based modeling of materials that are used in turbine blades, creep–fatigue interaction must be incorporated into characterization of turbine blade materials. PWA1484, a second generation single crystal nickel-base superalloy that is used for turbine blades in many of today's high performance jet engines was tested in a creep–fatigue environment that is meant to simulate some conditions of the service environment of a jet engine. This research explores the behavior and microstructural evolution of samples of PWA1484 tested in a creep–fatigue environment at 871 °C in air. It was found that specimens subjected to prior fatigue loading exhibit a smaller region of primary creep that is proportional to the number of prior fatigue cycles, and an accelerated transition to a tertiary creep regime. However, specimens that are subject to a static load and allowed to creep to 2.5% creep strain exhibited an un-affected fatigue behavior. Post-test microstructural analysis revealed a coarsening of the gamma prime ( γ′) precipitates that was dependent on loading condition and time spent at elevated temperature.

Using Evolutionary Algorithms for Signal Integrity Assessment of High-Speed Data Buses

Today's high performance computer systems must have fast, reliable access to memory and I/O devices. Unfortunately, inter-symbol interference, transmission line effects and other noise sources can distort data transfers. Engineers must therefore determine if bus designs have signal integrity--i.e., can transfer data with minimal amplitude or timing distortion. One method of determining signal integrity on buses is to conduct a set of data transfers and measure various signal parameters at the receiver end. But the tests must be conducted with stressful test patterns that maximize noise to help identify any potential problems. In this paper we describe how an evolutionary algorithm was used to evolve test patterns for use in intrinsic testing.

A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation

As power consumption and the corresponding heat dissipated on a die grow rapidly, efficient on-chip temperature regulation becomes imperative for today's high performance microprocessors. Temperature tracking based on the on-chip thermal sensors is not sufficient as the temperature hot spots keep changing with the load. One way to mitigate this problem is by means of software sensors, where temperature of any location is computed based on realtime power information and calibrated with the physical sensors. In this paper, we present a very efficient numerical thermal analysis method, which is suitable for fast temperature tracking and runtime thermal regulation. The proposed method, called FEKIS, combines two existing numerical techniques: extended Krylov subspace reduction technique to reduce the thermal circuit complexity and large-step integration method to exploit the sampled-based power input traces, which is typical in the power traces at the architectural and operation system levels. Experimental results show that FEKIS archives 10x speedup over recently proposed state-of-the art thermal moment matching technique 1,2 and the precise time-step integration method only, and three orders of magnitude faster than the traditional numerical integration method with high accuracy.

Characterization of a Novel Nine-Transistor SRAM Cell

Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 X as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.

Optical Detection of SiN Stress Layer Induced Carrier Mobility Enhancement in Silicon

ABSTRACTStrain engineering is key element for improving MOSFET device performance in today's advanced high performance microelectronics. Strained SiN layers are well established in this regard to generate near surface strain effects for carrier mobility enhancement. Non destructive detection of effects from strain layers has not been resolved yet, especially during the processing of patterned wafers. Since optical reflective measurements are well established for non destructive thickness measurements in semiconductor manufacturing, the signals out of those spectra can be used to investigate stress induced carrier mobility enhancement effects, as shown in this work. This provides direct access to the effectiveness of the applied near surface strain to the carrier mobility. By this novel method, SiN films at different stress levels and under different process conditions are investigated on silicon bulk wafers. On these wafers, the optically detected spectra shift, known as plasmon shift, can be correlated with standard wafer bow stress measurement results. These results are correlated to the electrical performance of microelectronic test structures. Based on this, the relative variation of the stress levels of SiN films after different process treatments, and the impact on carrier mobility in microelectronic devices is shown.

An Approach To Data Distributions in Chapel

A key characteristic of today's high performance computing systems is a physically distributed memory, which makes the efficient management of locality essential for taking advantage of the performance enhancements offered by these architectures. Currently, the standard technique for programming such systems involves the extension of traditional sequential programming languages with explicit message-passing libraries, in a processor-centric model for programming and execution. It is commonly understood that this programming paradigm results in complex, brittle, and error-prone programs, because of the way in which algorithms and communication are inextricably interwoven. This paper describes a new approach to locality awareness, which focuses on data distributions in high-productivity languages. Data distributions provide an abstract specification of the partitioning of large-scale data collections across memory units, supporting coarse-grain parallel computation and locality of access at a high level of abstraction. Our design, which is based on a new programming language called Chapel, is motivated by the need to provide a high-productivity paradigm for the development of efficient and reusable parallel code. We present an object-oriented framework that allows the explicit specification of the mapping of elements in a collection to memory units, the control of the arrangement of elements within such units, the definition of sequential and parallel iteration over collections, and the formulation of specialized allocation policies as required for advanced applications. The result is a concise high-productivity programming model that separates algorithms from data representation and enables reuse of distributions, allocation policies, and data structures.

Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?

In today's high performance (multi-GHz) microprocessors' design, on-chip clock calibration features are needed to compensate for electrical parameter variations as a result of manufacturing process variations. The calibration features allow performance boost after manufacturing test and maintain such performance levels during normal operation, thus preserving product quality. This strategy has been proven successful commercially. In this paper, we discuss the impact on performance and product quality of both permanent and transient faults possibly affecting these calibration circuits during manufacturing and normal operation, respectively. In particular, we consider the case of an on-chip clock calibration feature of a commercial high performance microprocessor. We will show that some possible permanent faults may render the on-chip clock calibration schemes useless (in process variations' compensation), while it is impossible for common manufacturing testing to detect this incorrect behavior. This means that a faulty operating microprocessor may pass the testing phase and be put onto the market, with a consequent impact on product quality and increase in Defect Level. Similarly, we will show that some possible transient faults occurring during the microprocessor in-field operation could defeat the purpose of on-chip clock calibration, again resulting in faulty operation of the microprocessor. This has long range implications to microprocessors' design as well, considering that process variations on die, as well as across the process, would worsen with continued scaling. Proper strategies to test these clock calibration features and to guarantee their correct operation in the field cannot be ignored. Possible design approaches to solve this problem will be discussed.

Thin film resonator technology

Advances in wireless systems have placed increased demands on high performance frequency control devices for operation into the microwave range. With spectrum crowding, high bandwidth requirements, miniaturization, and low cost requirements as a background, the thin film resonator technology has evolved into the mainstream of applications. This technology has been under development for over 40 years in one form or another, but it required significant advances in integrated circuit processing to reach microwave frequencies and practical manufacturing for high-volume applications. This paper will survey the development of the thin film resonator technology and describe the core elements that give rise to resonators and filters for today's high performance wireless applications.

Advances in VLSI testing at MultiGb per second rates

Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps). Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability) methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment) resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator) patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.

Recursive Blocked Algorithms and Hybrid Data Structures for Dense Matrix Library Software

Matrix computations are both fundamental and ubiquitous in computational science and its vast application areas. Along with the development of more advanced computer systems with complex memory hierarchies, there is a continuing demand for new algorithms and library software that efficiently utilize and adapt to new architecture features. This article reviews and details some of the recent advances made by applying the paradigm of recursion to dense matrix computations on today's memory-tiered computer systems. Recursion allows for efficient utilization of a memory hierarchy and generalizes existing fixed blocking by introducing automatic variable blocking that has the potential of matching every level of a deep memory hierarchy. Novel recursive blocked algorithms offer new ways to compute factorizations such as Cholesky and QR and to solve matrix equations. In fact, the whole gamut of existing dense linear algebra factorization is beginning to be reexamined in view of the recursive paradigm. Use of recursion has led to using new hybrid data structures and optimized superscalar kernels. The results we survey include new algorithms and library software implementations for level 3 kernels, matrix factorizations, and the solution of general systems of linear equations and several common matrix equations. The software implementations we survey are robust and show impressive performance on today's high performance computing systems.

Recursive blocked algorithms for solving triangular systems—Part II

We continue our study of high-performance algorithms for solving triangular matrix equations. They appear naturally in different condition estimation problems for matrix equations and various eigenspace computations, and as reduced systems in standard algorithms. Building on our successful recursive approach applied to one-sided matrix equations (Part I), we now present novel recursive blocked algorithms for two-sided matrix equations, which include matrix product terms such as AXB T . Examples are the discrete-time standard and generalized Sylvester and Lyapunov equations. The means for achieving high performance is the recursive variable blocking, which has the potential of matching the memory hierarchies of today's high-performance computing systems, and level-3 computations which mainly are performed as GEMM operations. Different implementation issues are discussed, including the design of efficient new algorithms for two-sided matrix products. We present uniprocessor and SMP parallel performance results of recursive blocked algorithms and routines in the state-of-the-art SLICOT library. Although our recursive algorithms with optimized kernels for the two-sided matrix equations perform more operations, the performance improvements are remarkable, including 10-fold speedups or more, compared to standard algorithms.

Fast priority queues for cached memory

The cache hierarchy prevalent in todays high performance processors has to be taken into account in order to design algorithms that perform well in practice. This paper advocates the adaption of external memory algorithms to this purpose. This idea and the practical issues involved are exemplified by engineering a fast priority queue suited to external memory and cached memory that is based on &lt;i&gt;k&lt;/i&gt;-way merging. It improves previous external memory algorithms by constant factors crucial for transferring it to cached memory. Running in the cache hierarchy of a workstation the algorithm is at least two times faster than an optimized implementation of binary heaps and 4-ary heaps for large inputs.