Timing, Trigger And Control System Research Articles

A new data transfer scheme for the HL-LHC upgrade of the ATLAS Tile Hadronic Calorimeter

The Large Hadron Collider (LHC) is undergoing a series of upgrades towards a High Luminosity LHC (HL-LHC) that will deliver five times the LHC nominal instantaneous luminosity. The ATLAS experiment is one of the experiments at the LHC that investigates elementary particle interactions in collisions of high-energy proton beams. To prepare for data taking in high-luminosity conditions, the ATLAS Tile Hadronic Calorimeter (TileCal) will replace completely on- and off-detector electronics using a new read-out architecture. The TileCal detector signals will be digitized by on-detector electronics and transferred to the TileCal PreProcessors (TilePPr), which comprise the main component of the off-detector electronics. In the TilePPr, the digitized data will be stored in pipeline buffers and be packed and read out to the Front-End LInk eXchange (FELIX) system upon the reception of a trigger decision. FELIX is a new detector readout component being developed as part of the ATLAS upgrade effort. FELIX is designed to act as a data router between the data acquisition detector control and TTC (Timing, Trigger and Control) systems and the new or updated trigger and detector front-end electronics. Whereas previous detector readout implementations relied on diverse custom hardware platforms, the idea behind FELIX is to unify all readout across one well supported and flexible platform.

The FELIX detector interface for the ATLAS TDAQ upgrades and its deployment in the ITk demonstrator setup

The ATLAS experiment at the LHC at CERN will move to use the Front-End Link eXchange (FELIX) system in a staged approach for LHC Run 3 (2021) and LHC Run 4 (2026). FELIX will act as the interface between the data acquisition; detector control and TTC (Timing, Trigger and Control) systems; and new or updated trigger and detector front-end electronics. FELIX functions as a router between custom serial links from front end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX also forwards the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network run innovative multi-threaded software for event fragment building, processing, buffering and forwarding. This proceeding will describe the design and status of the FELIX based readout for the Run 3 upgrade, during which a subset of the detector will be migrated. It will also show how the same concept has been successfully introduced into the demonstrator test bench of the ATLAS Pixel Inner Tracker, acting as a proof of concept towards the longer term Run 4 upgrade in which all detectors will adopt a FELIX based readout.

FELIX: the new detector interface for ATLAS

After the current LHC shutdown (2019-2021), the ATLAS experiment will be required to operate in an increasingly harsh collision environment. To maintain physics performance, the ATLAS experiment will undergo a series of upgrades during the shutdown. A key goal of this upgrade is to improve the capacity and flexibility of the detector readout system. To this end, the FrontEnd Link eXchange (FELIX) system has been developed. FELIX acts as the interface between the data acquisition; detector control and TTC (Timing, Trigger and Control) systems; and new or updated trigger and detector front-end electronics. The system functions as a router between custom serial links from front end ASICs and FPGAs to data collection and processing components via a commodity switched network. The serial links may aggregate many slower links or be a single high bandwidth link. FELIX also forwards the LHC bunchcrossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. FELIX uses commodity server technology in combination with FPGA-based PCIe I/O cards. FELIX servers run a software routing platform serving data to network clients. Commodity servers, connected to FELIX systems via the same network, run the new multi-threaded Software Readout Driver (SW ROD) infrastructure for event fragment building, buffering and detector-specific processing to facilitate online selection. This presentation will cover the design of FELIX and the results of the installation and commissioning activities for the full system.

FELIX: the new detector interface for the ATLAS experiment

During the next major shutdown from 2019-2020, the ATLAS experiment at the LHC at CERN will adopt the Front-End Link eXchange (FELIX) system as the interface between the data acquisition, detector control and TTC (Timing, Trigger and Control) systems and new or updated trigger and detector front-end electronics. FELIX will function as a router between custom serial links from front end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX will also forward the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers will run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network will run the new Software Readout Driver (SW ROD) infrastructure for event fragment building and buffering, with support for detector or trigger specific data processing, and will serve the data upon request to the ATLAS High-Level Trigger for Event Building and Selection. This proceeding will cover the design and status of FELIX and the SW ROD.

FELIX: the New Detector Interface for the ATLAS Experiment

During the next major shutdown (2019-2020), the ATLAS experiment at the LHC will adopt the Front-End Link eXchange (FELIX) system as the interface between the data acquisition, detector control and TTC (Timing, Trigger and Control) systems and new or updated trigger and detector front-end electronics. FELIX will function as a router between custom serial links from front-end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX will also forward the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers will run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network will run the new Software Readout Driver (SW ROD) infrastructure for event fragment building and buffering, with support for detector or trigger specific data processing, and will serve the data upon request to the ATLAS High Level Trigger for Event Building and Selection. This paper will cover the design and status of FELIX, the SW ROD, results of early performance testing and integration tests with several ATLAS front-ends.

A micro-TCA based data acquisition system for the Triple-GEM detectors for the upgrade of the CMS forward muon spectrometer

The Gas Electron Multiplier (GEM) upgrade project aims at improving the performance of the muon spectrometer of the Compact Muon Solenoid (CMS) experiment which will suffer from the increase in luminosity of the Large Hadron Collider (LHC). The GEM collaboration proposes to instrument the first muon station with Triple-GEM detectors, a technology which has proven to be resistant to high fluxes of particles. The architecture of the readout system is based on the use of the microTCA standard hosting FPGA-based Advanced Mezzanine Card (AMC) and of the Versatile Link with the GBT chipset to link the on-detector electronics to the micro-TCA boards. For the front-end electronics a new ASIC, called VFAT3, is being developed. On the detector, a Xilinx Virtex-6 FPGA mezzanine board, called the OptoHybrid, has to collect the data from 24 VFAT3s and to transmit the data optically to the off-detector micro-TCA electronics, as well as to transmit the trigger data at 40 MHz to the CMS Cathode Strip Chamber (CSC) trigger. The microTCA electronics provides the interfaces from the detector (and front-end electronics) to the CMS DAQ, TTC (Timing, Trigger and Control) and Trigger systems. In this paper, we will describe the DAQ system of the Triple-GEM project and provide results from the latest test beam campaigns done at CERN.

The NA62 Liquid Krypton calorimeter readout architecture

The NA62 experiment [1] at the CERN SPS (Super Proton Synchrotron) accelerator studies the ultra-rare decays of charged kaons. The high-resolution Liquid Krypton (LKr) electromagnetic calorimeter of the former NA48 experiment [2] is a key component of the experiment photon-veto system. The new LKr readout system comprises 14,000 14-bit ADC acquisition channels, 432× 1 Gbit Ethernet data request and readout links routed by 28× 10 Gbit network switches to the experiment computer farm, and timing, trigger and control (TTC) distribution system. This paper presents the architecture of the LKr readout and TTC systems, the overall performance and the first successfully collected experiment physics data.

A TTC upgrade proposal using bidirectional 10G-PON FTTH technology

A new generation FPGA-based Timing-Trigger and Control (TTC) system based on emerging Passive Optical Network (PON) technology is being proposed to replace the existing off-detector TTC system used by the LHC experiments. High split ratio, dynamic software partitioning, low and deterministic latency, as well as low jitter are required. Exploiting the latest available technologies allows delivering higher capacity together with bidirectionality, a feature absent from the legacy TTC system. This article focuses on the features and capabilities of the latest TTC-PON prototype based on 10G-PON FTTH components along with some metrics characterizing its performance.

Metrics and methods for TTC-PON system characterization

A new generation FPGA-based Timing, Trigger and Control (TTC) system based on emerging Passive Optical Network (PON) technology is being investigated to potentially replace the existing off-detector TTC system used by the LHC experiments. The new system must deliver trigger and data with low and deterministic latency as well as a recovered bunch clock with picosecond-level jitter. This new topology offers major improvements over its predecessor: bi-directionality as well as higher capacity. This paper focuses on the figures of merit used to characterize the TTC-PON system both downstream and upstream, on the techniques used to extract them and on the impact of these first results in optimizing the architecture.

Design, implementation and test of the timing trigger and controlreceiver for the LHC

The Timing Trigger and Control (TTC) system is an opticalnetwork which distributes the timing and synchronization signals of theLarge Hadron Collider (LHC) machine to the LHC experiments. It is also usedto transmit the trigger information of each experiment to the on-detectorelectronics. The TTC system has been designed in the late 90's, by usingVLSI processes available at that time. Thus, some elements of the system arenow obsolete and, in particular, only a small number of the networkreceivers (TTCrx) is presently available to be deployed in the LHCexperiments. In this paper we describe a possible implementation of theTTCrx, which should be used to replace the TTCrx chips on the off-detectorelectronics, where radiation is not a concern. Our design is based on theXilinx Virtex-5 FPGAs, and uses fabric resources and embedded high speedserial link transceivers, in order to emulate the architecture and the mainfeatures of the TTCrx. By using our approach, the receiver part of the TTCcan be easily implemented in commercial FPGAs, thus resulting in a fastdesign implementation, a simple layout and a cost-effective solution. Inthis paper, we present the details of the implementation and the testresults.

Implementation of the timing, trigger and control system of the CMS experiment

This paper presents the implementation of the Timing, Trigger and Control (TTC) system of the CMS Experiment currently under construction at CERN. The TTC system distributes the system clock for the experiment as well as the first level Triggers and synchronization commands. The overall system is described, highlighting the differences from the original concept of the CERN RD-12 collaboration in terms of overall system architecture. Details are given of the two VME-format electronics boards that implement the necessary functionality required by the system design changes.