Abstract

The ATLAS experiment at the LHC at CERN will move to use the Front-End Link eXchange (FELIX) system in a staged approach for LHC Run 3 (2021) and LHC Run 4 (2026). FELIX will act as the interface between the data acquisition; detector control and TTC (Timing, Trigger and Control) systems; and new or updated trigger and detector front-end electronics. FELIX functions as a router between custom serial links from front end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX also forwards the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network run innovative multi-threaded software for event fragment building, processing, buffering and forwarding. This proceeding will describe the design and status of the FELIX based readout for the Run 3 upgrade, during which a subset of the detector will be migrated. It will also show how the same concept has been successfully introduced into the demonstrator test bench of the ATLAS Pixel Inner Tracker, acting as a proof of concept towards the longer term Run 4 upgrade in which all detectors will adopt a FELIX based readout.

Highlights

  • The ATLAS experiment [1] will undergo a series of upgrades known as Phase-I (2019) and Phase-II (2024) to cope with the increase in luminosity expected for the LHC Run 3 (2021) and LHC Run 4 (2026)

  • These upgrades will result in an increase of two orders of magnitude in the number of electronic channels that the Trigger and Data AQcuisition (TDAQ) system will have to read out

  • Upgrades of the ATLAS DAQ System The ATLAS DAQ system during Run 2 was based on custom point to point links from the different sub-detector front-end electronics to the Read-out Driver (ROD)

Read more

Summary

Introduction

The ATLAS experiment [1] will undergo a series of upgrades known as Phase-I (2019) and Phase-II (2024) to cope with the increase in luminosity expected for the LHC Run 3 (2021) and LHC Run 4 (2026). 2. Upgrades of the ATLAS DAQ System The ATLAS DAQ system during Run 2 was based on custom point to point links from the different sub-detector front-end electronics to the Read-out Driver (ROD).

Results
Conclusion
Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call