Time-to-digital Converter Circuit Research Articles

Development and test of a next-generation positron detector

This report is focused on the development and test of a TDC (time to digital converter) and amplifier circuit for a state-of-the-art positron detector with position sensitivity. A newly developed one chip amplifier-shaper-discriminator (ASD) circuit with 16 channels input and a high-resolution TDC with a timing resolution on the order of picoseconds were tested. Silicon photomultipliers (SiPMs) were employed to give electric pulses for the optical input coming from a pulsed laser. We have successfully controlled the threshold level of the ASD circuit and measured the time structure of the SiPMs, as well as their multiple photon response from the pulse height histogram and the time over the threshold (TOT) histogram measured by the sub-nano second TDC. This is a technical basis for the next generation detector system with the positron tracking capability.

A 13.42ps Resolution, Low-Power Time-to-Digital Converter and 0.519fJ Energy-Efficient Novel Voltage-to-Time Converter for High-Speed Time-Based ADC Application

Voltage domain ADC architectures require high gain and high bandwidth opamps to amplify the signal for successive stages. The opamp design gets a bit challenging due to noise, small gain and lower overdrive voltage. Due to these limitations, the inclination shifted towards high-speed converters which don’t require opamps. Time based Analog to Digital Converters (TBADC) is one such category of circuits. TBADCs are constituted from VTC followed by TDC with an encoder in the end. This work is concerned around the design of a high-resolution time to digital converter (TDC) and proposing a novel high-speed, low power consuming voltage to time converter (VTC) circuit. Both the circuits were implemented in Cadence Virtuoso EDA tool version 6.1.7 and Spectre was employed for running the simulations. TDC circuits had resolution of 13.425 ps and consume power of 1.873 μW. Process corner analysis and Monte Carlo analysis were performed on VTC design to determine worst possible deviations in performance. The proposed VTC exhibited delay of 23.79 ps with power consumption of 21.83 μW at 1 Volt. The presented TDC and VTC circuits can be used to design high-speed time-based Analog to Digital Converters.

A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs.

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.

A Low-Power Time-to-Digital Converter for Sensor Interface Circuits

This brief proposes a new low-power time-to-digital converter (TDC). In contrast to the previous works that digitize each new input sample independent of the previous ones, the proposed structure obtains the digital code of the new sample based on the difference between the previous sample and the new one. Therefore, since the activity of the circuit is reduced, its power consumption is saved, especially for the applications that the variation of the input signal is usually much smaller than the signal range, such as sensor interface circuits. Based on the proposed structure, a 200 kS/s TDC circuit with a resolution of 3.2 ps is designed and simulated in a 65-nm CMOS technology. Post-layout simulation results show that the proposed structure achieves an effective number of bits (ENOB) of 7.52 bits at the cost of 10.1 μW power consumption. Moreover, the effective area occupied by the circuit is 110 μm × 130 μm.

A Low-Power Multichannel Time-to-Digital Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR Sensors

This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through a coarse counter, middle, and fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle and fine all-digital delay-locked loops (ADDLLs) is provided to ensure the stability of the generated time slots. Charge pump, loop filter, and voltage-controlled delay line inside the conventional analog delay-locked loops (DLLs) are replaced by an accumulator (ACC) and digitally controlled delay line (DCDL). This makes the design particularly compact, low power, and suitable for multichannel applications. The presented architecture can generate information for amplitude variation (walk error) compensation. This information is generated by measuring the pulsewidth and position of three successive STOP pulses inside each channel within a single-shot measurement. A low-jitter injection-locked frequency multiplier (ILFM) generates a 625-MHz internal clock signal out of 25-MHz external reference oscillator, which shrinks the number of delay elements to cover one period of the reference clock and improves the precision of the TDC. Operation at higher frequency provides high throughput and short conversion time (less than 3 ns). The three-level TDC offers 13.1- $\mu \text{s}$ maximum input range and 50-ps resolution. The measured DNL and INL of the TDC circuit are 0.47 and 0.71 LSB, respectively. The TDC circuit is implemented in a 180-nm standard CMOS process with a die size of 1.5 mm $\times1.5$ mm. The total power consumption of the multichannel TDC is 87.6 mW.

Compact laser radar based on a subnanosecond laser diode transmitter and a two-dimensional CMOS single-photon receiver

A pulsed TOF laser radar utilizing the single-photon detection mode has been implemented, and its performance is characterized. The transmitter employs a QW double-heterostructure laser diode producing 0.6 nJ/100 ps laser pulses at a central wavelength of ∼810 nm. The detector is a single-chip IC manufactured in the standard 0.35-μm HV CMOS process, including a 9×9 single-photon avalanche diode (SPAD) array and a 10-channel time-to-digital converter (TDC) circuit. Both the SPAD array and the TDC circuit support a time gating feature allowing photon detection to occur only within a predefined time window. The SPAD array also supports a 3×3 SPADs subarray selection feature to respond to the laser spot wandering effect due to the paraxial optics and to reduce background radiation-induced detections. The characterization results demonstrate a distance measurement accuracy of +/−0.5 mm to a target at 34 m having 11% reflectivity. The signal detection rate is 28% at a laser pulsing rate of 100 kHz. The single-shot precision of the laser radar is ∼20 mm (FWHM). The deteriorating impact of high-level background radiation conditions on the SNR is demonstrated, as also is a scheme to improve this by means of detector time gating.

Low‐power TDC scheme using DLL‐based gray counter for infrared imagers

A low-power time-to-digital converter (TDC) scheme for column-level single-slope analogue-to-digital converters for infrared imager is presented. This scheme greatly improves the TDC's timing precision with a novel 3-bit fine gray counter, which makes use of multi-phase clocks from a delay-lock-loop. Aimed for 384 × 288 array size uncooled infrared imager with 17 μm pixel pitch, the TDC circuits have been developed and simulated employing 0.18 μm CMOS technology. Compared with conventional two-step TDC methods, this method saves more chip area and reduces the sampling power consumption by >50%, and also eliminates the coarse-fine inconsistency problem with a simulated ±0.1 least-significant-bit differential non-linearity performance.

Dual-time resolution time-based transceiver for low-power serial interfaces

A dual-time resolution differential-time signaling (DTR-DTS) architecture is proposed in this paper. The number of transmitted bits per symbol in a time-based serial link can be increased by using dual-time resolution pulse-position modulation at the transmitter side instead of using the conventional pulse-position modulation without significantly affecting the transmitted signal bandwidth. Using the proposed architecture, the receiver design is simplified by using time-to-digital converter (TDC) circuits with less number of bits compared to the differential-time signaling (DTS) architecture for the same link rate. The design details are presented in this paper. A simulated 8-bit 12 Gb/s DR-DTS link has been designed in 65 nm mixed signal CMOS process using Cadence tools. Four TDC circuits, 2-bits each, have been used to recover the 8-bits from the received signal. The simulated DTR-DTS link consumes 3.6 mW without the driver circuit.

A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology

A gated ring oscillator (GRO) based time-to-digital converter (TDC) is presented. To enhance the resolution of the TDC, a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2. The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm2. According to the measurement results, the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range, the maximum clock frequency of this circuit is larger than 200 MHz. Under a 1 V power supply, with a 200–800 ps input time difference, the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

This paper proposes a method for testing delay faults using a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC.

Wide-Range Time-to-Digital Converter With 1-ps Single-Shot Precision

A high-resolution time-to-digital converter (TDC) was designed and tested. The converter is based on the fundamental method of counting the full clock cycles of a low-phase-noise reference clock and using a single-stage interpolating method employing time-to-amplitude converters that are based on Miller integrators. Counters and other control logic were implemented on a field-programmable gate array, and the interpolation units were constructed using discrete components. The single-shot precision of the uncompensated converter is about 1.8 ps over a time interval range of 0 to 328 μs. Single-shot precision is limited by the nonlinearities of the interpolators. These measurement errors caused by the nonlinearities are systematic, and thus, precision can be improved to 1 ps by a simple integral nonlinearity compensation. Other important factors that contribute to single-shot precision are the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -cycle jitter of the reference clock and the noise generated by the TDC circuit itself. By careful design, these errors can be made small enough to achieve picosecond-level precision.

Comparison of TDC Circuit Design Method to Constant Delay Time

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

Delay Time Reliability of Analog and Digital Delay Elements for Time-to-Digital Converter

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

A Multihit Time-to-Digital Converter Architecture on FPGA

We present a multihit time-to-digital converter (TDC) architecture implemented in a field-programmable gate array (FPGA) with minimized timing overhead. The TDC circuit provides two-level fine-time interpolation. The fine interpolator is a matrix of Vernier delay cells interconnected in a topology to provide two propagation paths for the incoming data pulse. Two methods of calibration are presented to estimate the component delays. The TDC circuit achieves time measurements with a resolution of 75 ps with an average precision of ~ 300 ps and is capable of detecting incoming pulses at a distance of 7.5 ns or more from each other.

Time-to-digital converters based on RSFQ digital counters

We have designed, fabricated, and successfully tested a Time-to-Digital converter (TDC). The TDC circuit consists of superconductive counters based on toggle flip-flops with destructive readout, shift registers, parallel-to-serial converters, and pulse detectors. The value of the counter is latched while the counter is operating at full speed. The TDC resolution is directly determined by the maximum counter speed, or 50 ps for an available 20 GHz clock rate. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 kA/cm/sup 2/ using HYPRES' library of standard RSFQ cells.

A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

Phase-locked loops have been employed in the past to obtain sub-nanosecond time resolution in high energy physics and nuclear science applications. An alternative solution based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C-element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multichannel, time-to-digital converter (TDC) targeted for one specific frequency. The two circuits, DLL and TDC, are implemented in CMOS 1.21 /spl mu/m and 0.8 /spl mu/m technologies, respectively. Test results show a timing jitter of less than 30 ps for the DLL circuit and less than 190 ps integral and differential non-linearity for the TDC circuit.