Timing Mismatch Errors Research Articles

A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity

In front of the offset, gain, timing, and bandwidth mismatch errors, time-interleaved analog-to-digital converters (TIADCs) are usually calibrated to achieve satisfying performance. In this paper, we propose a new digital calibration approach for TIADCs, including the direction-distance search algorithm and multiplier-free gradient descent method. Compared to state-of-the-art multiplication-less techniques, this approach significantly reduces time complexity by minimizing search space dimension, subtracting the number of searches, and varying iteration step size. Notably, no multiplier is needed in the mismatch estimation, resulting in a much lower computational complexity than in previous work. For a 12-bit 4-channel TIADC, simulation results show that the signal-to-noise-and-distortion ratio is improved from 25 dB to 65 dB within the duration of 1600 samples. The proposed calibration circuit is synthesized targeting standard 28-nm technology, occupying the area of 0.014 mm2 and dissipating the power of 19 mW at 2.8 GHz clock frequency.

A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm

Timing-mismatch errors among channels in time-interleaved analog-to-digital converters (TIADCs) greatly degrade the whole performance of the system. Therefore, techniques for calibrating timing mismatch are indispensable, and a new fully-digital calibration technique is presented in this article. Based on a Hilbert filter, modified moving averagers (MMAs) and inverse cosine functions, the proposed estimation algorithm is fast (within 1200 sample points) and accurate. Meanwhile, the coordinate rotational digital computer (CORDIC) algorithm, which is used to implement inverse cosine functions, is also improved, giving it higher precision. In addition, a compensation method based on second-order Taylor series approximation with less hardware resource consumption is provided. Through analyses and simulations, this calibration technique proved to be suitable for TIADCs with an arbitrary number of channels, in which the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were, respectively, improved from 24.06 dB and 24.57 dB to 67.96 dB and 85.69 dB.

A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters

Mismatch-based nonlinear distortion greatly influences the accuracy and spurious-free dynamic range (SFDR) of current steering digital-to-analog converters (CS-DACs). Dynamic element matching (DEM) is an intelligent technique that reduces both amplitude and timing mismatch errors. In conventional DEM DACs, further enhancement of SFDR at higher frequencies is constrained due to the presence of intersegment mismatch errors in separate segmented structures. In this article, a pairwise swap enabled randomized DEM (PSER-DEM) technique is proposed to address the intersegment mismatch effect in segmented CS-DAC. This technique uses both randomization and swapping between row and column elements of current source cells for selecting the unit current source elements. A 6-bit CS-DAC with the PSER-DEM technique has been implemented with the UMC 180-nm 1.8-V CMOS process. The proposed DAC architectures with circuit description and measurement results are demonstrated briefly. A 48.15-dB SFDR with more than 6-dB enhancement is achieved from the measurement result. The proposed architecture for 10-bit CS-DAC is presented with vigorous mismatch-based Monte Carlo simulation results, which shows more than 70-dB SFDR for the entire Nyquist range frequency with more than 7-dB improvement from the conventional DEM DACs. Along with the PSER-DEM technique, a signal-dependent randomization concept is proposed to reduce the element transition rate and switching activity of current cells, which reduced the power consumption up to 4 mW for oversampling DACs. A comparative assessment is presented with state-of-the-art literature on DEM DAC structures. The proposed method has exhibited superior performance, which signifies the suitability for high-speed and high-resolution CS-DACs.

All-digital calibration algorithm based on channel multiplexing for TI-ADCs

An adaptively calibration structure featured by channel multiplexing that can simultaneously calibrate the offset, gain, and timing mismatch errors existing in TI-ADC (Time-Interleaved ADC) channels in pure digital domain is proposed, which focuses on the problem of limited input signal bandwidth and high calibration hardware overhead. In error compensation aspect, these three mismatch errors are compensated simultaneously by adaptive method. The gain mismatch compensation employed here can help to overcome the deviation that would exist when the first-order Taylor compensation was employed alone for the timing mismatch, which can significantly improve the calibration effect in high-frequency band instead of employing complex high-order Taylor compensation structure. The total calibration algorithm is implemented using FPGA. For the 4-channel, 1 GS/s and 14-bit TI-ADC, the signal-to-noise distortion ratio (SNDR) of the system is increased from 26.19 dB to 84.37 dB, and the spurious free dynamic range (SFDR) is increased from 29.35 dB to 98.49 dB when the input signal normalized frequency f in / f s is 0.975.

An estimation method of timing mismatch error in hybrid filter bank DACs

An estimation method of timing mismatch error in hybrid filter bank DACs

Joint Compensation of Jitter Noise and Time-Shift Errors in Multichannel Sampling System

In high-speed analog-to-digital converters (ADCs), two main factors contribute to high power consumption. The first is the super linear relationship with the sampling rate; i.e., by doubling the sampling rate, the power consumption more than doubles. The second factor arises from the consumption of analog circuitry responsible to mitigate the jitter noise. By employing a multichannel sampling system, one can achieve high sampling rates by incorporating multiple low sampling-rate channels, which results in a linear scaling of power consumption with the number of channels. The main drawback of this system is the timing mismatch between the sampling channels. In this paper, we intend to jointly compensate the jitter noise and the timing mismatch between the channels using statistical methods. We first approximate the acquisition system and derive a stochastic model. Then, we propose an iterative maximum likelihood algorithm to estimate the parameters of the input signal. We further evaluate the Cramer-Rao lower bound (CRLB) for the estimation error to examine the proposed algorithm. Simulation results indicate that our algorithm is capable of closely following the CRLB curve for reasonable values of jitter noise and a wide range of timing mismatch errors. Moreover, it is shown that the mismatch-compensated multichannel sampling system performs almost equivalently to a single-channel high rate sampler without having its shortcomings.

Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC

Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 19.27 dB and 35.2 dB, respectively. This analysis was done for an input signal frequency of $$0.09f_s$$ . In the case of an input signal frequency of $$0.45f_s$$ , an improvement by 33.06 dB and 43.14 dB is respectively achieved in SNDR and SFDR. In addition to the simulation, the algorithm was implemented in hardware for real-time evaluation. The low computational burden of the algorithm allowed an FPGA implementation with a low logic resource usage and a high system clock speed (926.95 MHz for four channel algorithm implementation). Thus, the proposed architecture can be used as a post-processing algorithm in host processors for data acquisition systems to improve the performance of TIADC.

Joint background calibration of gain and timing mismatch errors with low hardware cost for time‐interleaved ADCs

A joint background calibration scheme is proposed for the gain and timing mismatch errors in time-interleaved analogue-to-digital converts (TI ADCs). Mixed-signal calibration is adopted for timing mismatch without using correlators or multi-tap digital filters, while the gain mismatch is estimated and calibrated all digitally based on the moving average of the derivative for each channel's output. Therefore, the influence of offset mismatch on the estimation accuracy of the gain error can be eliminated completely. To reduce hardware cost as much as possible, most of the arithmetic blocks are reused for gain and timing mismatch estimation. Behavioural simulation with a 12 bit, 2 GSPS two-channel TI ADC and measurement results from a commercial 12 bit 3.6 GSPS two-channel TI ADC show that the proposed joint calibration scheme can effectively correct the gain and timing mismatch errors.

Real-time self-adaptive calibration method for high speed acquisition system.

The main factors that enable capture of complex and transient signals in real-time are improved sampling rates and processing speeds. The time-interleaved architecture is an effective method that allows systems to break through the speed bottleneck of single analog-to-digital converters (ADCs) and go beyond the state-of-the-art process technology limit. However, the performance of the acquisition system may be reduced because of the offset, gain, and time mismatch errors that occur in time-interleaved ADC systems. To correct these errors, this paper first proposes a self-adaptive correction algorithm and then introduces real-time solutions for this algorithm. Finally, the proposed calibration method is implemented in a digital phosphor oscilloscope. Simulations and experimental testing indicate that this system shows good real-time performance and provides a high dynamic performance with an effective number of bits of 7.3 bits and a signal-to-noise ratio of 45.5574 dB.

Pilot-Based TI-ADC Mismatch Error Calibration for IR-UWB Receivers

In this work, we first provide an overview of the state of the art in mismatch error estimation and correction for time-interleaved analog to digital converters (TI-ADCs). Then, we present a novel pilot-based on-line adaptive timing mismatch error estimation approach for TI-ADCs in the context of an impulse radio ultra wideband (IR-UWB) receiver with correlation-based detection. We introduce the developed method and derive the expressions for both additive white Gaussian noise (AWGN) and Rayleigh multipath fading (RMPF) channels. We also derive a lower bound on the required ADC resolution to attain a certain estimation precision. Simulations show the effectiveness of the technique when combined with an adequate compensator. We analyze the estimation error behavior as a function of signal to noise ratio (SNR) and investigate the ADC performance before and after compensation. While all mismatches combined cause the effective number of bits (ENOB) to drop to 3 bits and to 6 bits when considering only timing mismatch, estimation and correction of these errors with the proposed technique can restore a close to ideal behavior. We also show the performance loss at the receiver in terms of bit error rate (BER) and how compensation is able to significantly improve performance.

A new adaptive blind background calibration of gain and timing mismatch for a two-channel time-interleaved ADC

This study investigates a new adaptive blind calibration structure for the calibration of gain and timing mismatch error, which is applied for a two-channel Time-Interleaved Analog-to-Digital Converter (TI-ADC). This technique calibrates the mismatch error in the output of the converter without any interrupt at the typical performance of the TI-ADC. The output of the time-interleaved ADC is approximated by modeling based on Taylor's series. The effect of gain and timing mismatch in the output is represented by the first order of Taylor's series. By using a Least-Mean Square (LMS) and correlation-based algorithm, the approximate coefficients of the Taylor's series are identified. Input signal and its chopped image or input signal and its chopped and delayed image will be correlated in the proposed algorithm. This algorithm can identify the coefficients blindly. It is simpler than the previous similar techniques. Also, this technique does not have the drawbacks of a technique which uses the Taylor's series approximation and filtered-X LMS algorithm. Simulation results confirm these claims and show that by entering six sinusoidal inputs in the whole bandwidth of the proposed technique, 48.2 dB improvement in Spur Free Dynamic Range (SFDR) is achieved.

All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters

This paper presents an all-digital background calibration for timing mismatch in time-interleaved analog-to-digital converters (TI-ADCs). It combines digital adaptive timing mismatch estimation and digital derivative-based correction, achieving lower hardware cost and better suppression of timing mismatch tones than previous work. In addition, for the first time closed-form exact expressions for the signal-to-noise and distortion ratio (SNDR) of a four-channel TI-ADC with timing mismatch after derivative-based digital correction are obtained, which can be used to guide the design. Simulation results of a four-channel TI-ADC behavioral model and measurement results from a commercial 12-bit 3.6-GS/s two-channel TI-ADC show that the proposed all-digital calibration can accurately estimate the timing skew and effectively correct the timing mismatch errors, while also confirming the analytic SNDR expressions.

Analysis of Channel Mismatch Errors in Frequency-Interleaved ADC System

Frequency-interleaved ADC (FIADC) is less sensitive to the mismatches between channels than the time-interleaved ADC (ADC). However, channel mismatches in FIADC such as offset, gain, and timing mismatches among channel ADCs still degrade the performance of the FIADC system. This paper analyzes the channel mismatch effects in the FIADC system. Based on the analysis, we have clarified that the gain mismatch errors and timing mismatch errors result in noises with the same frequency but different phases, and only the magnitudes of noises due to the offset mismatch errors do not depend on the input frequency. The analyzed results can be used for calibration algorithms to compensate for the channel mismatch errors among the FIADC channels.

A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

This paper presents a 14 bit 200 MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range. Compared to traditional current source calibration techniques and static-mismatch mapping, DMM can reduce the distortion caused by both amplitude and timing mismatch errors. Compared to dynamic element matching, DMM does not increase the noise floor since the distortion is reduced, not randomized. The DMM DAC was implemented in a 0.14 μm CMOS technology and achieves a state-of-the-art performance of SFDR >; 78 dBc, IM3 <; -83 dBc and NSD <; -163 dBm/Hz in the whole 100 MHz Nyquist band.

Phase extraction based efficient timing mismatch identification in time-interleaved analogue-to-digital converter systems

An efficient timing mismatch identification technique based on phase extraction for M-channel time-interleaved analogue-to-digital converters is presented. Identification using a test tone with frequency up to the system Nyquist band in a reduced frequency domain computation is described. It is demonstrated that the proposed technique is computationally efficient and can accurately estimate timing mismatch errors.

Analysis and Implementation of a Time-Interleaved ADC Array for a Software-Defined UWB Receiver

A software-defined radio (SDR) for ultrawideband (UWB) communication systems places several stringent requirements on the analog-to-digital converter (ADC). One alternative to using a single ADC is to sample the received signal with an array of lower speed ADCs that were driven by interleaved sampling clocks; however, mismatches among the ADCs will result in signal distortion. This paper makes three important contributions to overcoming this problem: 1) analytical quantification of the impact of ADC gain, offset, and timing mismatches on the performance of a time-interleaved sampling ADC array for UWB signals; 2) demonstration of the efficacy of using a pilot-based matched-filter architecture to mitigate the impact of timing mismatches in the presence of multipath; and 3) implementation of an 8-ADC time-interleaved UWB SDR testbed that operates at an effective sampling frequency of 6.4 GHz. In addition, our findings allow for the design specification of the number of pilots required to obtain a desired system performance. The simulation and measured performance results from this paper demonstrate that ADC mismatches can be controlled to within plusmn10%, yielding acceptable levels of distortion and bit-error-rate (BER) performance on the UWB SDR testbed. Both analytical and simulation results also demonstrate the efficacy of a pilot-based matched filter in mitigating the impact of timing mismatch errors, even in the presence of multipath.

Blind Calibration of Timing Skew in Time-Interleaved Analog-to-Digital Converters

The performance of time-interleaved analog-to-digital converters is often significantly degraded by timing mismatch errors. We develop methods for performing blind calibration of such converters, i.e., for estimating the unknown time-skew parameters and for performing signal reconstruction from these estimates. The methods are low in complexity and allow for accurate calibration in systems with large numbers of converters, provided that the skews are sufficiently small in magnitude. We also present modifications to calibrate gain mismatch as well as adaptive sequential methods of implementation. Performance and complexity analysis is provided to support the viability of the methods.

Blind equalization of time errors in a time-interleaved ADC system

To significantly increase the sampling rate of an analog-to-digital converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the time mismatch errors. The estimation method requires no knowledge about the input signal, except that it should be band limited to the foldover frequency /spl pi//T/sub s/ for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the time errors. The Cramer-Rao bound (CRB) for the time error estimates is also calculated and compared to Monte Carlo simulations. The estimation method has also been validated on measurements from a real time-interleaved ADC system with 16 ADCs.

Analysis of mismatch effects in a randomly interleaved A/D converter system

Time interleaving can be used to significantly increase the sampling rate of an ADC system. However, the problem with time interleaving is that the ADCs are not exactly identical. This means that time, gain and offset mismatch errors are introduced in the ADC system, which cause nonharmonic distortion in the sampled signal. One way to decrease the impact of the mismatch errors is to spread the distortion over a wider frequency range by randomizing the order in which the ADCs are used in the interleaved structure. In this paper we analyze how the spectrum is affected by mismatch errors in a randomly interleaved ADC system. We also discuss how the mismatch errors can be estimated.

Blind Adaptive Equalization of Mismatch Errors in a Time-Interleaved A/D Converter System

To significantly increase the sampling rate of an A/D converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the mismatch errors. The estimation method requires no knowledge about the input signal except that it should be bandlimited to the Nyquist frequency for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the mismatch errors. The estimation method has been validated with simulations and measurements from a time-interleaved ADC system.