Time-interleaved ADC System Research Articles

Analysis and design of M-channel frequency-interleaved ADC with analog filter estimation

Compared to time-interleaved ADC system, the performance of frequency-interleaved ADC (FIADC) system is extremely sensitive to the parameter uncertainties of the analog analysis filters. In this paper, a new method is launched to estimate the amplitude and phase responses of the analog analysis filters, which will help us grasp the actual filter status in real applications. Then, two algorithms are presented to obtain the digital synthesis filters aiming at minimize the reconstruction error. Design example and verification results show that the analysis filters can be estimated effectively and the designed synthesis filters meet the need of the FIADC system.

Researches on Channel Mismatch Effects in Time-Interleaved ADC System

The Time-Interleaved ADC（TIADC) is an effective method for implement ultra high-speed data acquisition. However, the errors of channel mismatch are seriously degrade the signal-to-noise ratio of the system, such as Time-skew error, Gain error and Offset error. This paper have done some researches and analysis, and given the modeling of the three channels mismatch. What's more, it also given a detailed analysis of error and the method of measure it, derived the formula of signal to noise and distortion ratio(SINAD) and spurious free dynamic range(SFDR). All of them provide a reference for the tolerance range of TIADC channel mismatch error. Meanwhile, the result of this paper has provided a theoretical basis for eliminating TIADC channel mismatch error.

Research of Channel Dismatch Errors in Parallel AD Acquisition System Based on FPGA

With the development of modem broadband radar, amount of reaserchers focus on broadband radar echo signal acquisitions and feature extraction of the target. Due to the large bandwidth as high as several MHz, the time interleaved ADC system is playing an important in radar echo systems, but this structure will bring in channel dismatch errors. The paper gave an explicit analysis of such three channel mismatch errors, and established the formulas of spectrum when all three mismatch errors exist together. Then presented the measure errors algorithm combined three errors according to the formulas of spectrum and the effective calibration algorithm．The algorithm was implemented in FPGA at last.

Multi-tone sine wave fit algorithm of channel time delay in time-interleaved ADC system

Multi-tone sine wave fit algorithm of channel time delay in time-interleaved ADC system

A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth

A new sample-and-hold (S&H) architecture is proposed for time-interleaved analog-to-digital converter (ADC). The use of this S&H circuit in front-end of a time-interleaved ADC system eliminates the need for sample-time calibration. Using the techniques of precharging and output capacitor coupling along with a new sampling technique called middle-plate-sampling can mitigate the stringent performance requirements for the opamp and sampling switches, resulting in low power consumption and allowing very high sampling rate. Simulated by HSPICE with a standard BSIM3v3 0.18 mum technology, the S&H achieves 10-12 bits resolution for a 1.6-V pp output at 1-GHz sampling rate. The S&H dissipates 12 mW from a 1.8-V supply.

A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs

Sample-time error among the channels of a time-interleaved analog-to-digital converter (ADC) is the main reason for significant degradation of the effective resolution of the high-speed time-interleaved ADC. A calibration technique for sample-time mismatches has been proposed and implemented at a low level of complexity. The calibration method uses random data and is especially suitable for ADCs used in digital data communication systems. An 800-MS/s four-channel, time-interleaved ADC system has been implemented to evaluate the performance of the technique. The experimental results show that the spurious-free dynamic range of the ADC system is improved to 58.1 dB at 350 MHz. The ADC system achieves a signal-to-noise and distortion ratio of 59.6 dB at 5 MHz and 50.1 dB at 350 MHz after calibration.

Blind equalization of time errors in a time-interleaved ADC system

To significantly increase the sampling rate of an analog-to-digital converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the time mismatch errors. The estimation method requires no knowledge about the input signal, except that it should be band limited to the foldover frequency /spl pi//T/sub s/ for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the time errors. The Cramer-Rao bound (CRB) for the time error estimates is also calculated and compared to Monte Carlo simulations. The estimation method has also been validated on measurements from a real time-interleaved ADC system with 16 ADCs.