Time-dependent Breakdown Research Articles

Mechanism of frequency-dependent gate breakdown in p-GaN/AlGaN/GaN HEMTs

In this Letter, time-dependent gate breakdown (TDB) characteristics under dynamic switching conditions were investigated in p-GaN/AlGaN/GaN high-electron-mobility transistors (HEMTs) with either Schottky-type or Ohmic-type gates. The dynamic TDB of the Schottky-type devices increased with frequencies ranging from 100 Hz to 100 kHz, while that of the Ohmic-type devices remained frequency-independent. This was analyzed by the frequency-dependent electroluminescence (EL) characteristics on both types of devices with semi-transparent gate electrodes. The electroluminescence (EL) emission intensity of Schottky-type devices increased with elevated frequencies, notably for blue and ultraviolet emissions, which exhibited a pronounced positive correlation with frequency. In contrast, the EL emissions of Ohmic-type devices were frequency-independent. Energy band diagrams were drawn to explain the different TDB and EL behaviors between two types of devices. The frequency-enhanced EL emissions of the Schottky-type devices indicated the frequency-enhanced hole injection and radiative recombination, which then suppressed the hot-electron effects on the metal/p-GaN junction and enhanced the dynamic TDB in p-GaN/AlGaN/GaN HEMTs.

The Gate Oxide Breakdown Failures of 4H-SiC MOS Devices

A study of Weibull distribution of 4H-SiC MOS capacitors has shown the effect of temperature as well as electric-field stress on the analysis of time-dependent breakdown. Time-Dependent Dielectric Breakdown (TDDB) is strongly electric-field dependent and temperature-dependent. In the paper, the test was at the stress level of 9.5, 10, and 10.5 MV/cm under 373K, through the TDDB model, the lifetime of the SiO2 can reach more than 30 years when the field pressure is not more than 6.6 MV /cm. The acceleration factor for TDDB (using E-Model) under different temperature stress, it expected that the capacitors would last for 2.28×107 years under 3MV/cm or 54 years under 6MV/cm at 373K.

Research on reliability of complementary metal oxide semiconductor integrated circuit

Complementary metal oxide semiconductor (CMOS) devices are an important part of integrated circuit (IC), but in the application process, it has many reliability problems, such as negative-bias temperature instability (NBTI), electromigration (EM), time-dependent gate oxide breakdown (TDDB), hot carrier injection (HCI), etc. These reliability problems can affect the threshold voltage and mobility of the device. In order to improve the reliability of integrated circuits, these reliability problems are systematically studied in this paper.

Comprehensive Investigation of Constant Voltage Stress Time-Dependent Breakdown and Cycle-to-Breakdown Reliability in Y-Doped and Si-Doped HfO2 Metal-Ferroelectric-Metal Memory.

In this study, we comprehensively investigate the constant voltage stress (CVS) time-dependent breakdown and cycle-to-breakdown while considering metal-ferroelectric-metal (MFM) memory, which has distinct domain sizes induced by different doping species, i.e., Yttrium (Y) (Sample A) and Silicon (Si) (Sample B). Firstly, Y-doped and Si-doped HfO2 MFM devices exhibit domain sizes of 5.64 nm and 12.47 nm, respectively. Secondly, Si-doped HfO2 MFM devices (Sample B) have better CVS time-dependent breakdown and cycle-to-breakdown stability than Y-doped HfO2 MFM devices (Sample A). Therefore, a larger domain size showing higher extrapolated voltage under CVS time-dependent breakdown and cycle-to-breakdown evaluations was observed, indicating that the domain size crucially impacts the stability of MFM memory.

Revealing the Mechanism of the Bias Temperature Instability Effect of p-GaN Gate HEMTs by Time-Dependent Gate Breakdown Stress and Fast Sweeping Characterization.

The bias temperature instability (BTI) effect of p-GaN gate high-electron-mobility transistors (HEMTs) is a serious problem for reliability. To uncover the essential cause of this effect, in this paper, we precisely monitored the shifting process of the threshold voltage (VTH) of HEMTs under BTI stress by fast sweeping characterizations. The HEMTs without time-dependent gate breakdown (TDGB) stress featured a high VTH shift of 0.62 V. In contrast, the HEMT that underwent 424 s of TDGB stress clearly saw a limited VTH shift of 0.16 V. The mechanism is that the TDGB stress can induce a Schottky barrier lowering effect on the metal/p-GaN junction, thus boosting the hole injection from the gate metal to the p-GaN layer. This hole injection eventually improves the VTH stability by replenishing the holes lost under BTI stress. It is the first time that we experimentally proved that the BTI effect of p-GaN gate HEMTs was directly dominated by the gate Schottky barrier that impeded the hole supply to the p-GaN layer.

Crosslinked and Multi-Responsive Polymeric Vesicles as a Platform to Study Enzyme-Mediated Undocking Behavior: Toward Future Artificial Organelle Communication.

Various cellular functions are successfully mimicked, opening the door to the next generation of therapeutic approaches and systems biology. Herein, the first steps are taken toward the construction of artificial organelles for mimicking cell communication by docking and undocking of cargo in the membrane of swollen artificial organelles. Stimuli-responsive and crosslinked polymeric vesicles are used to allow docking processes at acidic pH at which ferrocene units in the swollen membrane state can undergo desired specific host-guest interaction using β-cyclodextrin as model cargo. The release of the cargo mediated by two different enzymes, glucose oxidase and α-amylase, is investigated, triggered by distinct enzymatic undocking mechanisms. Different release times for a useful transport are shown that can be adapted to different communication pathways. In addition, Försterresonanceenergytransfer(FRET) experiments further support the hypotheses of host-guest inclusion complexation formation and their time-dependent breakdown. This work paves a way to a platform based on polymeric vesicles for synthetic biology, cell functions mimicking, and the construction of multifunctional cargo delivery system.

A survey of elastase-producing bacteria and characteristics of the most potent producer, Priestia megaterium gasm32.

Ninety-one elastase-producing bacterial isolates were recovered from different localities of the Eastern Province of Saudi Arabia. Elastase from the best isolate Priestia megaterium gasm32, from luncheon samples was purified to electrophoretic homogeneity using DEAE-Sepharose CL-6B and Sephadex G-100 chromatographic techniques. The recovery was 17.7%, the purification fold was 11.7x, and the molecular mass was 30 kDa. Enzymatic activity was highly repressed by Ba2+ and almost completely lost by EDTA, but it was greatly stimulated by Cu2+ ions, suggesting a metalloprotease type. The enzyme was stable at 45°C and pH 6.0-10.0 for 2 hours. Ca2+ ions considerably enhanced the stability of the heat-treated enzyme. The Vmax and Km against the synthetic substrate elastin-Congo red were 6.03 mg/mL, and 8.82 U/mg, respectively. Interestingly, the enzyme showed potent antibacterial activity against many bacterial pathogens. Under SEM, most bacterial cells showed loss of integrity, damage, and perforation. SEM micrographs also showed a time-dependent gradual breakdown of elastin fibers exposed to elastase. After 3 hours, intact elastin fibers disappeared, leaving irregular pieces. Given these good features, this elastase may be a promising candidate for treating damaged skin fibers with the inhibition of contaminating bacteria.

Investigation of the Progressive Gate Breakdown Behaviors in p-GaN Gate HEMTs

In this work, multiple time-dependent gate breakdown (BD) experiments are performed on p-GaN gate high-electron-mobility transistors (HEMTs) under constant gate voltage stress. Progressive gate BD behaviors are observed during the time-dependent failure process. It is found that the time-to-BD ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{\text {BD}}$ </tex-math></inline-formula> ) has a positive dependence on temperature but a weak relevance to p-GaN gate length. Moreover, it is confirmed that the Schottky junction first (1st) degenerates after the 1st stage jump of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{G}$ </tex-math></inline-formula> and the p-i-n junction fails in the subsequent process. The underlying failure mechanisms are revealed by further analyzing the degradation behaviors and the carrier transport mechanisms before/after the Schottky junction degrades. Hole Fowler–Nordheim (FN) tunneling at the metal gate/p-GaN interface guides the first degradation of the Schottky junction. Afterward, the trap-assisted electron tunneling across the AlGaN layer indicates the failure of the p-i-n junction. These two processes sequentially facilitate defect generation within the p-GaN and the AlGaN layer, resulting in a percolation path between the gate and the source terminal.

Revenue Management for Reusable Products with Time-Dependent Returns and Breakdowns

Purpose An arriving customer requests a product, and a firm makes an accept/reject decision. If accepted, the firm rents out the product and the customer uses it for a random duration of time and returns it to the firm. The returned product is used by other customers. These products are called reusable products. The product may be returned with breakdowns. Unlike the previous papers, this paper considers returns and breakdowns that depend on the rental duration. Methods For the optimal control, a dynamic programming model is formulated. Its state variable keeps track of the number of products for each rental duration to consider those time-dependent rates. To deal with the computational complexity, this paper develops a heuristic based on the linear programming model. Results In the numerical study, the paper shows that the revenue gain using the optimal policy reduces as the initial capacity increases whereas the computational time increases significantly. However, the heuristic produces a near-optimal solution for a large capacity within a short time interval. Conclusion Therefore, the heuristic is recommended especially when a firm has a large initial capacity.

The Role of Frequency and Duty Cycle on the Gate Reliability of p-GaN HEMTs

In this letter, we present an extensive analysis on the role of both switching frequency (ranging from 100 kHz to 1 MHz) and duty cycle (from 10% to 90%) on the time-dependent gate breakdown of high electron mobility transistors (HEMTs) with Schottky metal to p-GaN gate. More specifically, results show how the gate lifetime of GaN HEMTs increases by reducing the frequency and the duty cycle of the stressing gate signal (VG). Such behavior is ascribed to the OFF-time, which is responsible to alter the electrostatic potential in the p-GaN layer during the rising phases of VG (from OFF- to ON-state). Findings of this analysis are useful both for further technology improvement and for GaN-based power circuit designers.

Simulation of time to failure of porous dielectric in advanced topology integrated circuit metallization system

In this work, the simulation of the processes of diffusion of metal barrier ions into a low-k dielectric between two nearby copper lines was performed. Based on experimental data on the diffusion coefficient published in the scientific literature and calculations according to the mathematical model of the distribution of metal barrier ions in the dielectric, the time dependent breakdown of a porous low-k dielectric in the elements of very large-scale integrated circuits of the modern topological level was estimated. Additionally, the work obtained dependences of the dielectric breakdown time on the distance between two nearby copper lines along with dependence on the power voltage of the line (the other line is grounded).

P-GaN Gate HEMTs With 10.6 V Maximum Gate Drive Voltages by Mg Doping Engineering

We present a novel p-gallium nitride (GaN) gate HEMT structure with reduced hole concentration near the Schottky interface by doping engineering in metal-organic chemical vapor deposition (MOCVD), which aims at lowering the electric field across the gate. By employing the additional unintentionally doped GaN (u-GaN) layer, the gate leakage current is suppressed and the gate breakdown voltage is boosted from 10.6 to 14.6 V with negligible influence on the threshold voltage and ON-resistance. A reduced Mg concentration in the u-GaN layer was confirmed by secondary-ion mass spectrometry. Time-dependent gate breakdown measurements reveal that the maximum gate drive voltage increases from 6.2 to 10.6 V for a ten-year lifetime with a 1&#x0025; gate failure rate, which effectively expands the operating voltage margin of the p-GaN gate HEMTs without any other additional process step.

Optimizing Ferroelectric and Interface Layers in HZO-Based FTJs for Neuromorphic Applications

Nonvolatile memories especially the ferroelectric (FE)-based ones such as ferroelectric tunnel junctions (FTJs) and ferroelectric field-effect transistors (FeFETs) have recently attracted a lot of attention. FTJs have been intensively researched for the last decade and found to be very promising memory devices due to their significant nondestructive readout advantage as compared to conventional ferroelectric random access memory (FRAM). However, more research is needed on FTJ devices to obtain reliable endurance and retention behavior. In this article, we demonstrate the characteristics and performance of zirconium-doped hafnium oxide-based FTJ devices in terms of FE switching and reliability. This is investigated for FTJ stack structure tuning as well as for the FE switching process in FTJ devices. The FTJ memory switching characteristics, the effects of polarization switching on the write conditions, and the impact of pulse width and pulse amplitude on switching are investigated. The impact of FE layer thickness and interface layer type/thickness are reported to obtain a maximum FTJ <inline-formula> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio (memory window) and reliable performance. The maximum <inline-formula> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio changes depending on the FE layer (zirconium-doped HfO₂ layer) thickness (12, 8, 6, and 4 nm), the interface layer type (SiO₂, Al₂O₃), and thickness (1 and 2 nm), indicating the maximum value of <inline-formula> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio for a 1 nm SiO₂ interface layer stack. Moreover, a stable endurance of 10⁴ cycles is reported and extrapolated measurements suggest stable retention for more than ten years. Time-dependent breakdown analysis was performed to investigate the reliability of devices indicating a lifetime of ten years.

High-Temperature Time-Dependent Gate Breakdown of p-GaN HEMTs

In this article, we present an in-depth high-temperature analysis of the long-term gate reliability in GaN-based power high-electron-mobility transistors (HEMTs) with p-type gate. Three different isolation process options, aimed at improving the time-dependent gate breakdown (TDGB), are proposed and compared by means of constant voltage stress tests performed at different forward gate biases, temperatures, and geometries. In particular, depending on the gate bias and temperature, the breakdown event may occur along the active gate area or through the isolation region. The results show different voltage dependency for such two different failure locations; therefore, two field-acceleration fitting models are needed for the estimation of lifetime. Furthermore, the gate time-to-failure (TTF) shows a non-monotonous temperature dependency at given gate bias. More specifically, a positive and a negative T-derivatives are observed at relatively low and high temperatures, respectively, which are related to active gate area and isolation region failure, respectively.

Characterization of GaON as a surface reinforcement layer of p-GaN in Schottky-type p-GaN gate HEMTs

The surface of the p-GaN layer in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) can be reinforced with enhanced immunity to hot electron bombardment by reconstructing the surface region of p-GaN into GaON. The surface region of p-GaN is treated by remote oxygen plasma and subsequently annealed at 800 °C, thereby becoming a thin crystalline gallium oxynitride (GaON) layer that will be in direct contact with the Schottky metal. The GaON exhibits a lower valence band maximum energy than that of the p-GaN, which leads to a higher Schottky barrier at the metal/GaON interface to holes and, thus, greatly suppresses the forward gate leakage. More importantly, with higher thermodynamic stability and a larger bandgap of ∼4.1 eV, the GaON reinforces the susceptible metal/p-GaN interface against the hot electrons and, thus, substantially enhances the long-term gate reliability of p-GaN gate HEMTs under forward bias stress. The high-temperature thermal process is indispensable for the surface reconstruction, without which the plasma oxidation only reduces the gate leakage but fails to prolong the time-dependent gate breakdown lifetime.

Reliability of p-GaN Gate HEMTs in Reverse Conduction

Synchronous buck converter comprises a low side (LS) and a high side (HS) switch, where the HS switch works in the first quadrant (forward conduction) whereas the LS switch works in the third quadrant (reverse conduction). However, the reliability of the p-GaN gate high electron mobility transistor (HEMT) in reverse conduction is unclear. In this work, a comprehensive evaluation of this conduction mode for 200-V HEMTs was conducted. First, devices were subjected to time-dependent breakdown (TDB) measurements. By comparing different device configurations, the time to failure (TTF) was found to only scale with the number of gate fingers instead of the gate width ${W}_{G}$ , proving the critical spots are the intersection of gate fingers over the N implantation isolation. The reverse operation voltage of ${V}_{DS}$ for ten years lifetime was extrapolated to be −5.4 V, corresponding to a failure of 0.01% and 100 gate fingers. Second, the devices were submitted to 200-V ${V}_{DS}$ OFF-state stress for 10 s, after which the reverse drain current saw a negligible degradation. Third, the reverse conduction of the HEMTs only showed a very limited deterioration after a long-time bias temperature instability (BTI) stress at ${V}_{DS} = - 5.5$ V and ${V}_{GS} = 0$ V. This work proves the p-GaN gate HEMTs bear a high reliability in reverse conduction, which can simplify the design of synchronous power system.

Impact of Structural and Process Variations on the Time-Dependent OFF-State Breakdown of p-GaN Power HEMTs

In this article, we present an extensive investigation of the time-dependent drain breakdown occurring in GaN-on-Si power HEMTs with p-GaN gate under long-term OFF-state stress. In particular, the time-dependent breakdown induced by high-temperature-reverse-bias stress is investigated as a function of different process and structural variations. Main results demonstrate that, by varying the gate-to-drain distance ( $\text{L}_{\mathrm{ GD}}$ ) and the field plates configuration, the physical location of failure changes as well. If $\text{L}_{\mathrm{ GD}}$ is relatively short ( $3~\mu \text{m}$ ), the time-dependent breakdown occurs through the GaN channel layer between drain and source. In this case, a thinner GaN layer significantly improves the device robustness to long-term OFF-state stress. If $\text{L}_{\mathrm{ GD}}$ is relatively long ( $\ge 4 ~\mu \text{m}$ ), the failure occurs between the two-dimensional electron gas (2DEG) and the source field plates. In this second case, the GaN layer thickness and $\text{L}_{\mathrm{ GD}}$ have no significant impact on the time-dependent breakdown, whereas the field plate lengths can be optimized to reduce the area exposed to high electric fields, hence limiting the probability of failure. Finally, the role of the AlGaN barrier layer has been analyzed as well. If $\text{L}_{\mathrm{ GD}} = 3 ~\mu \text{m}$ , a thinner AlGaN layer is preferred, whereas if $\text{L}_{\mathrm{ GD}} \ge 4 ~\mu \text{m}$ , a thicker layer with lower aluminum content gives rise to longer time to breakdown under OFF-State stress.

Determination of the Operating Time to Failure of a Sub-100-nm MOS Transistor Gate Dielectric Using Accelerated Tests

A gate dielectric is one of the key structural elements of submicron MOS transistors, on which the reliability of its operation depends. A breakdown of the dielectric leads to a loss in the functioning of the transistor and the failure of the entire IC or a malfunction in its operation. Therefore, special attention is paid to assess the defectiveness of a gate dielectric and its operating time to failure. In this study, the operating time to failure of the gate insulator of MOS transistors is determined based on the method of the time-dependent breakdown of the dielectric using the thermomechanical model (E models). The Weibull distribution obtained for the integrated failure distribution of a sample of technological test structures measured at high voltage and temperature is used as the statistics of the distribution of failures. The studies are performed on the test structures, which are MOS capacitors with the gate dielectric thickness of 5 nm. The test structures are created using the 65 nm serial technology and are placed in a test crystal together with the IC on one plate. Software is developed that allows accelerated measurements in the automatic mode. As a result of the studies, the parameters of the thermomechanical failure model are determined, and the dependences of the operating time to failure of the gate dielectric on the operating conditions are obtained. It is established that for the test structures under study, both full and partial breakdown of the dielectric can occur. This control method can be used to predict the long-term reliability of the gate dielectric of sub-100-nm MOS transistors and certify the technological processes of its production.

P-GaN Gate HEMT With Surface Reinforcement for Enhanced Gate Reliability

By deploying a surface reinforcement layer (SRL) at the interface between Schottky metal and p-GaN in the gate stack, a p-GaN gate high-electron-mobility transistor (HEMT) with enhanced gate reliability is demonstrated. Prior to the gate metal deposition, the SRL is formed by an oxygen-plasma treatment and a subsequent high-temperature annealing process (at 800 °C) that enables surface reconstruction. Such a process converts several nanometers of p-GaN near the surface into a crystalline GaON layer, which exhibits stronger immunity to hot electron bombardment. With nearly identical threshold voltage and ON-resistance, the p-GaN gate HEMT with SRL yields two orders of magnitude reduction in gate leakage current at ON-state and an increase from 10.5 V to 12.7 V in forward gate breakdown voltage. Time-dependent gate breakdown measurement reveals an increase from 5.9 V to 7.8 V in the maximum ON -state gate drive voltage for a 10-year lifetime with a 1 % gate failure rate, which effectively expands the operating voltage margin of the p-GaN gate power HEMT.

Role of the AlGaN barrier on the long-term gate reliability of power HEMTs with p-GaN gate

Forward gate constant voltage stress (CVS) has been performed on GaN-on-Si (200 mm) HEMTs with p-GaN gate, controlled by a Schottky metal-retracted/p-GaN junction, processed by imec with different gate process splits. In particular, the adoption of devices with a different magnesium (Mg) concentration in the p-GaN layer, AlGaN barrier thickness and AlGaN aluminium percentage (Al%), allowed us to identify the degradation of the AlGaN barrier as responsible for time-dependent gate breakdown at room temperature. Lowering the Al% of the barrier and the Mg concentration of the p-GaN layer leads to a longer gate lifetime, while an optimum AlGaN barrier thickness is identified at given Al%.