Time Delay Digital Tanlock Loop Research Articles

Spatiotemporal Dynamics of a Network of Coupled Time-Delay Digital Tanlock Loops

The time-delay digital tanlock loop (TDTLs) is an important class of phase-locked loop that is widely used in electronic communication systems. Although nonlinear dynamics of an isolated TDTL has been studied in the past but the collective behavior of TDTLs in a network is an important topic of research and deserves special attention as in practical communication systems separate entities are rarely isolated. In this paper, we carry out the detailed analysis and numerical simulations to explore the spatiotemporal dynamics of a network of a one-dimensional ring of coupled TDTLs with nearest neighbor coupling. The equation representing the network is derived and we carry out analytical calculations using the circulant matrix formalism to obtain the stability criteria. An extensive numerical simulation reveals that with the variation of gain parameter and coupling strength the network shows a variety of spatiotemporal dynamics such as frozen random pattern, pattern selection, spatiotemporal intermittency and fully developed spatiotemporal chaos. We map the distinct dynamical regions of the system in two-parameter space. Finally, we quantify the spatiotemporal dynamics by using quantitative measures like Lyapunov exponent and the average quadratic deviation of the full network.

Performance evaluation of the time delay digital tanlock loop architectures

This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the original TDTL and to enhance the overall performance of the particular systems. The limitations addressed in this article include the non-linearity of the phase detector, the restricted width of the locking range and the overall system acquisition speed. Each of the modified architectures was tested by subjecting the system to sudden positive and negative frequency steps and comparing its response with that of the original TDTL. In addition, the performance of all the architectures was evaluated under noise-free as well as noisy environments. The extensive simulation results using MATLAB/SIMULINK demonstrate that the new architectures overcome the limitations they addressed and the overall results confirmed significant improvements in performance compared to the conventional TDTL system.

BIFURCATION, CHAOS AND THEIR CONTROL IN A TIME-DELAY DIGITAL TANLOCK LOOP

This paper reports the detailed parameter space study of the nonlinear dynamical behaviors and their control in a time-delay digital tanlock loop (TDTL). At first, we explore the nonlinear dynamics of the TDTL in parameter space and show that beyond a certain value of loop gain parameter the system manifests bifurcation and chaos. Next, we consider two variants of the delayed feedback control (DFC) technique, namely, the time-delayed feedback control (TDFC) technique, and its modified version, the extended time-delayed feedback control (ETDFC) technique. Stability analyses are carried out to find out the stable phase-locked zone of the system for both the controlled cases. We employ two-parameter bifurcation diagrams and the Lyapunov exponent spectrum to explore the dynamics of the system in the global parameter space. We establish that the control techniques can extend the stable phase-locked region of operation by controlling the occurrence of bifurcation and chaos. We also derive an estimate of the optimum parameter values for which the controlled system has the fastest convergence time even for a larger acquisition range. The present study provides a necessary detailed parameter space study that will enable one to design an improved TDTL system.

Tanlock loop noise reduction using an optimised phase detector

This article proposes a time-delay digital tanlock loop (TDTL), which uses a new phase detector (PD) design that is optimised for noise reduction making it amenable for applications that require wide lock range without sacrificing the level of noise immunity. The proposed system uses an improved phase detector design which uses two phase detectors; one PD is used to optimise the noise immunity whilst the other is used to control the acquisition time of the TDTL system. Using the modified phase detector it is possible to reduce the second- and higher-order harmonics by at least 50% compared with the conventional TDTL system. The proposed system was simulated and tested using MATLAB/Simulink using frequency step inputs and inputs corrupted with varying levels of harmonic distortion. A hardware prototype of the system was implemented using a field programmable gate array (FPGA). The practical and simulation results indicate considerable improvement in the noise performance of the proposed system over the conventional TDTL architecture.

Synchronization of a renewable energy inverter with the grid

The design, mathematical analysis, and testing results of the architecture of a new all-digital phase-locked loop system for synchronizing a voltage source DC-AC single-phase inverter with the low voltage utility grid are presented. The system which is based on the time-delay digital tanlock loop was simulated using matlab/simulink and was tested by subjecting the grid voltage to various perturbations similar to those which can occur in a real power system, such as voltage sags and nonlinear distortion of the grid voltage waveform. Results indicate that even in the presence of such perturbations the system achieved and/or re-gained synchronization within 100 ms. The proposed system is all-digital and can be readily implemented using a field programmable gate array and easily embedded into a power inverter.

Digital tanlock loop architecture with no delay

This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional time-delay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using MATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed.

TDTL Based Frequency Synthesizers with Auto Sensing Technique

This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep the complete system in lock. The mechanism uses a frequency sensing structure to control critical TDTL parameters responsible for locking. Both integer and fractional multiples of the loop reference frequency are synthesized by the new architecture. The ability of the TDTL based frequency synthesizer to respond to sudden variations in the system input frequency is studied. The results obtained indicate the proposed synthesizer has a robust performance and is capable of responding to those changes provided that they are within the bounds of its locking region.

Fast Switching Fractional-N Frequency Synthesizer Architecture Using TDTL

This paper presents an efficient indirect fractional frequency synthesizer architecture based on the time delay digital tanlock loop. The indirect type frequency synthesis systems incorporate a low complexity high performance adaptation mechanism that enables them to remain in a locked state following the division process. The performance of the proposed fractional-N synthesizer under various input conditions is demonstrated. This includes sudden changes in the system input frequency as well as the injection of noise. The results of the extensive set of tests indicate that the fractional-N synthesizer, proposed in this work, performs well and is capable of achieving frequency divisions with fine resolution. The indirect frequency synthesizer also has a wide locking range and fast switching response. This is reflected by the system ability to regain its lock in response to relatively large variations in the input frequency within a few samples. The overall system performance shows high resilience to noise as reflected by the mean square error results.

Improved First-Order Time-Delay Tanlock Loop Architectures

This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation.

Time Delay Digital Tanlock Loop with Broad Lock Range Using Chaos Control Technique

The main objective of this paper is to broaden the lock range of the first order Time Delay Digital Tanlock Loop (TDTL) by extending the loop stable behaviour using a feedback stabilization to control the chaotic region of TDTL. The non-linear behaviour of TDTL shows a period doubling to its route to chaos. The loop has two or more fixed points depending on the values of the gain of loop filter and the input frequency offset from the locking value. The tendency of a TDTL to diverge is measured and fed-back as a form of linear stabilization. The lock range extension is confirmed through the use bifurcation diagrams and maximum Lyapunov exponents.

Convergence behavior of the first-order time-delay digital tanlock loop

Convergence behavior of the previously proposed time-delay digital tanlock loop (TDTL) is analyzed. The approach is built on the actual number of steps required for the convergence of the phase error to its steady-state value. Unlike the first-order conventional digital tanlock loop (CDTL), the Lipschitz bound of TDTL is not a tight limit for the actual convergence time, especially for higher values of the absolute difference between the initial and the steady-state phase errors. For a frequency step input, the first-order TDTL locks faster than CDTL under suitable arrangement of the loop parameters.

The time-delay digital tanlock loop: performance analysis in additive Gaussian noise

Recently, a new non-uniform sampling digital phase-locked loop, the time-delay digital tanlock loop (TDTL), has been proposed. We have analyzed in a previous work the first- and second-order TDTLs under noise-free conditions. In this work, we analyze the performance of the TDTL in the presence of additive Gaussian noise for different values of the loop parameters. It is shown that the expected value of the steady-state phase errors at the input and the output of the phase error detector are equal to the noise-free steady-state values, while the variance is significantly reduced when the signal-to-noise ratio is increased or the phase shift introduced by the time-delay approaches 90°. The locking ranges of the TDTL parameters under noise-free conditions are unchanged by the presence of noise.

A time-delay digital tanlock loop

We propose a nonuniform sampling digital tanlock loop (DTL) that utilizes a constant time-delay unit instead of the constant 90/spl deg/ phase shifter The new structure reduces the complexity of implementation and avoids many of the practical problems associated with the digital Hilbert transformer like the approximations and frequency limitations. The time-delay digital tanlock loop (TDTL) preserves the most important features of the conventional DTL (CDTL), such as reduced sensitivity to the variation of the signal power. It also introduces improvement over the first-order CDTL under suitable choice of the circuit parameters. The first- and second-order loops are analyzed for locking conditions and steady-state phase error.