Tight Output Research Articles

Derivation of Dual-Switch Step-Down DC/DC Converters With Fault-Tolerant Capability

This letter presents a graph-theoretic approach to deriving a family of dual-switch step-down dc/dc converters with fault-tolerant capability. The constraint sets in the derivation process ensure that minimum additional component is used to achieve fault-tolerant operation. The operation of converters derived is flexible. Under normal operating conditions, one of the two switches can serve as a main switch to control the power flow (i.e., single-switch converter operation) and the other switch is in stand-by mode. When a fault occurs on the main switch, the other switch will be activated to provide an alternate current path to continue converter operation and maintain output regulation. The fault-tolerant converters are derived by integrating a buck converter with a buck–boost converter. They share all the components except for the power switches. Due to different duty cycles required between the two operating conditions, a feedback controller is necessary to adjust the duty cycle for tight output regulation. The derivation procedure and experimental results on fault occurrence are reported. The converter derivation approach is able to identify reported topologies and can be extended to synthesize other topologies with fault-tolerant capability.

An Integrated High-Density Power Management Solution for Portable Applications Based on a Multioutput Switched-Capacitor Circuit

This paper introduces a novel power management architecture (PMA) and its on-chip implementation, designed for battery-powered portable applications. Compared to the conventional two-stage PMA, consisting of a front-end inductive converter followed by a set of point-of-load buck converters, the presented PMA has drastically improved power density. The new architecture, named multioutput switched-capacitor convertor–differential-input buck (MSC–DB) convertor, is based on a novel hybrid converter topology that combines a fixed ratio MSC and a set of DB converters, to achieve low volume and high power processing efficiency. The front-end switched-capacitor stage has a higher power density than the conventionally used inductive converters. The downstream DB converters enable tight output voltage regulation, and allow for up to four times reduction of output filter inductors without the need for increasing switching frequency, hence limiting switching losses and improving the efficiency of the system. Furthermore, the new PMA is able to balance the state-of-charge of the input battery cells, a feature not existing in conventional systems. The PMA architecture is implemented both as a discrete prototype and as an application-specific integrated circuit (IC) module. The on-chip implemented architecture is fabricated in a standard 0.13-μm CMOS process and operates at 9.3-MHz switching frequency. Experimental comparisons with a conventional two-cell battery input architecture, providing 15 W of total power in three different voltage outputs, demonstrate up to two times reduction in the inductances of the downstream converter stages and more than two times reduction in losses, equivalent to the improvement of the power processing efficiency of a 12%. Moreover, the fabricated IC module is copackaged with low-profile thin-film inductors to demonstrate the effectiveness of the introduced architecture in reducing the volume of PMAs for portable applications.

Self-Synchronized Universal Droop Controller

In this paper, a self-synchronization mechanism is embedded into the universal droop controller (UDC), which is applicable to inverters having an impedance angle between $-{\pi }/{2}$ rad and ${\pi }/{2}$ rad, to form a self-synchronized UDC (SUDC). Both the voltage loop and the frequency loop of the UDC are modified to facilitate the standalone and grid-connected operation of inverters. Importantly, the dedicated phase-locked-loop that is often needed for grid-connected or parallel-operated converters is removed. The inverter is able to achieve synchronization before and after connection without the need of a dedicated synchronization unit. Since the original structure of the UDC is kept in the SUDC, the properties of the UDC, such as accurate power sharing and tight output voltage regulation, are well maintained. Extensive experimental results are presented to demonstrate the performance of the proposed SUDC for a grid-connected single-phase inverter.

Fuzzy Gain Scheduling of PI Plus Derivative Controller to Improve the Transient Response of Boost DC/DC Converter

This paper illustrates a fuzzy gain scheduling of PI plus derivative controller. The proposed control technique improves the transient response of a DC/DC converter. The proposed control system is easy to implement based on an STM32F4 microcontroller. The performance evaluation was done by an experiment through a boost DC/DC converter, with a 24W load, a 12V input voltage, and a 24V output voltage, respectively. The system operation achieves tight output voltage regulation, both for the steady-state and transient responses.

Current‐sharing bus and fuzzy gain scheduling of proportional–integral controller to control a parallel‐connected AC/DC converter

In this study, a current-sharing bus and fuzzy gain scheduling of proportional–integral (PI) controller to control a parallel-connected AC/DC converter are proposed. A simple current-sharing circuit is applied to divide the load current to calculate the peak input current of each converter module. Fuzzy gain scheduling of PI controller is used to compensate for the error of the output voltage. The dsPIC30F6010 microcontroller is applied in the voltage loop control. In addition, a hysteresis control circuit is used to control the current loop. The experimental performance evaluation is conducted on a prototype, with three converter modules that are parallel-connected, has 250 W/module and has a −48 V DC output voltage. The system offers the following advantages: the tight output voltage regulates both the steady-state operation and the transient response. The current sharing is quite good, and it is simpler to operate in the redundant mode.

Field‐programmable gate array‐based linear–non‐linear control with high‐resolution digital pulse width modulator and high‐speed embedded analogue‐to‐digital converter for multi‐phase voltage regulator modules

Power converters for applications with high switching frequency and tight output voltage regulation such as voltage regulator modules (VRM) for microprocessors power supplies require fast dynamic response to meet the specifications. An existing control technique known as linear-non-linear (LnL) control strategy allows improving the transient converter response by means of an easy rule for the saturation of the duty cycle. The use of a digital implementation can optimise the transient response of the multi-phase VRM with LnL. However, digital control leads to other problems derived from time discretisation and finite word length effects. The limited resolution and the sampling delay are critical issues for digital control implementation of multi-phase VRM with LnL control. As a result, a high-resolution digital pulse width modulator (DPWM) and high-speed analogue-to-digital (A/D) converter are required to obtain proper performance of the converter. This study is focused on the digital implementation of the well-known LnL control in a multi-phase VRM taking advantage of low-cost field-programmable gate array resources. A detailed description of the digital implementation of the main converter control blocks, which are the A/D converter, the compensator and the DPWM, is provided in the paper.

Applying Reduced General Direct Space Vector Modulation Approach of AC–AC Matrix Converter Theory to Achieve Direct Power Factor Controlled Three-Phase AC–DC Matrix Rectifier

This paper presents a novel approach to achieve both tight dc voltage regulation and direct power factor control by applying general direct space vector modulation (G-SVM) of matrix converter theory to a three-phase ac–dc matrix rectifier. The reduced form of G-SVM and the derivation of the three-phase ac–dc matrix rectifier from a three-phase ac–ac matrix converter are described and theoretically justified. The proposed matrix converter features intrinsic buck conversion, tight output voltage regulation via modulation, inherent capability of four-quadrant operation, elimination of the bulky storage component on the dc bus, and sinusoidal input current. Moreover, the reduced G-SVM-controlled three-phase ac–dc matrix rectifier can achieve leading, lagging, or unity input power factor by simple and direct control of the input current displacement angle. This significantly benefits the potential application of the reduced G-SVM-controlled three-phase matrix rectifier to automotive, aircraft, ship, and other three-phase standby dc supplies. In these applications, the unity power factor control is indispensable when the dc load widely changes. Simulated and experimental verification for this strategy has been presented and discussed in this paper.

Technique to Improve the Transient Response of Parallel-Connected AC/DC Converters

In this paper, a technique to improve the transient response of a parallel-connected AC/DC converter has been studied. The proposed technique is used to improve the transient response while disturbance is injected into the system. Generally, a conventional voltage loop control uses a PI controller, because of which a slow transient response is observed. In this paper, the voltage loop control is composed of a signal from the PI controller added with a peak input current and gain scheduling of change in peak input current. The performance evaluation was experimented on a three-module isolated CUK AC/DC converter, with a 500W load and-48V DC output voltage. The system achieves the following: tight output voltage regulation, good current sharing, and low harmonic distortion. Moreover, the disturbance occurs in the system by an immediate load change, and the output voltages are at minimum overshoot and undershoot with a fast settling time.

Modeling, Control, and Implementation of DC–DC Converters for Variable Frequency Operation

In this paper, novel small-signal averaged models for dc-dc converters operating at variable switching frequency are derived. This is achieved by separately considering the on-time and the off-time of the switching period. The derivation is shown in detail for a synchronous buck converter and the model for a boost converter is also presented. The model for the buck converter is then used for the design of two digital feedback controllers, which exploit the additional insight in the converter dynamics. First, a digital multiloop PID controller is implemented, where the design is based on loop-shaping of the proposed frequency-domain transfer functions. And second, the design and the implementation of a digital LQG state-feedback controller, based on the proposed time-domain state-space model, is presented for the same converter topology. Experimental results are given for the digital multiloop PID controller integrated on an application-specified integrated circuit in a 0.13 μm CMOS technology, as well as for the state-feedback controller implemented on an FPGA. Tight output voltage regulation and an excellent dynamic performance is achieved, as the dynamics of the converter under variable frequency operation are considered during the design of both implementations.

Comments: The Embargo at 40

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A soft‐switching post‐regulator for multi‐outputs dual forward DC/DC converter with tight output voltage regulation

An improved soft-switching post-regulator topology for multi-outputs dual forward DC/DC converter is presented. A delay-trailing modulation method is proposed. ZVSZCS on/zero-current-switching off conditions can be realised on both the primary MOSFETs and the secondary rectifying diodes. Excellent decoupling among different outputs and tight output voltage regulation are achieved. The efficiency is improved due to single power-conversion stage and share in the primary components. The operating principle and main feature of this improved topology are analysed. Key design issue including zero-voltage-switching operation, maximum duty ratio of the primary side MOSFETs and parameter determination for the primary magnetising inductor and the secondary additional redistribution capacitor are discussed. Finally, an experimental prototype with two outputs (300–400 V input, 48 V, 6.5 A and 24 V, 11 A outputs) is built to verify the theoretical analysis. The measured efficiency at normal operation input voltage (400 V) is improved by about 0.5–2%, and the measured efficiency under light loads is improved by more than 2%.

On the Computation of Output Bounds for Compartmental In-Series Models under Parametric Uncertainty

In this work, the problem of obtaining tight output bounds for compartmental in-series models under parametric uncertainty is addressed. It is well-known that current methods used to compute a solution envelope may produce a significant overestimation. However, monotonicity analysis enables us to estimate a tight solution envelope. Our main aim is to get an equivalent model to the initial one, which is usually non-monotone, by means of a suitable combination of equations. In this new model the system monotonicity with respect to the uncertain parameters depends on the elimination rate values of the original model. If the equivalent model is monotone, no overestimation occurs in the computation of the output bounds.

Impact of Linear–Nonlinear Control in Multiphase VRM Design

The new generation of microprocessors has imposed more demanding design requirements for their power supplies, usually known as voltage regulator modules (VRM). The transient response of the converter is a critical design issue since tight output voltage regulation should be achieved at lower voltage values and higher current levels with faster transient slew rates. In order to meet the new specifications, multiphase interleaved synchronous buck converters are the most interesting solution from the VRM design viewpoint since this power topology allows increasing the current level minimizing the total equivalent inductance and the output capacitor. Regarding the converter control strategy, an existing control technique known as linear-nonlinear control improves the converter transient response with an easy saturation rule of the duty cycle since it is based on output voltage sensing. As a consequence, a reduction of the number of phases and the switching frequency of the multiphase VRM is obtained. This paper analyzes the impact of the reduction of the number of phases and switching frequency on the converter size in comparison with multiphase VRM with linear control strategy.

Flyback-Based Single-Stage Power-Factor-Correction Scheme With Time-Multiplexing Control

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A flyback-based single-stage power-factor-correction scheme with time-multiplexing control (TMC) is proposed. As a portion of the input power will be transferred to the output after the first power processing to improve the conversion efficiency, the output voltage would contain substantial low-frequency ripple. An isolated auxiliary circuit based on forward topology is therefore added to the converter to serve as a buffer and a ripple suppression circuit. With TMC, all the power processes can be achieved by a single transformer to lower the size and cost of the converter. In addition, the proposed converter inherits bulk capacitor (auxiliary) voltage clamping capability. The experimental results confirmed the effectiveness of the proposed scheme with high power factor, natural bulk capacitor (auxiliary) clamping voltage, and tight output regulation. </para>

Robust and Nonlinear Controller for a Unity Power Factor Rectifier

The problem of controlling full bridge AC/DC switched power converters commonly addressed as power factor correctors of Boost type is considered. The control objective consists in keeping the input power factor close to unity, regulating the output voltage and to ensure an adequate robustness against uncertainties of the converter parameters. The control law is designed from the large-signal bilinear model of the converter using the robust version of backstepping technique. The obtained regulator is shown to meet its objectives namely a tight output voltage regulation, a power factor correction, and robustness with respect to component uncertainties

HOPF BIFURCATION AS AN INTERMEDIATE-SCALE INSTABILITY IN SINGLE-STAGE POWER-FACTOR-CORRECTION POWER SUPPLIES: ANALYSIS, SIMULATIONS AND EXPERIMENTAL VERIFICATION

This paper reports intermediate-scale instability in a single-stage power-factor-correction (PFC) power supply that employs a cascade configuration of a boost stage operating in discontinuous conduction mode (DCM) and a forward stage operating in continuous conduction mode (CCM). The two stages combine into a single stage by sharing one main switch and one control loop to achieve input PFC and tight output regulation. The main results are given by "exact" cycle-by-cycle circuit simulations. The effect of the intermediate-scale instability on the attainable power factor is illustrated in terms of total harmonic distortion (THD) which is found by taking the Fast Fourier Transform (FFT) of the input current. The intermediate-scale instability usually manifests itself as local oscillations within a line cycle. Based on the stability analysis of a buck converter operating in CCM, the underlying mechanism of such instability can be attributed to the Hopf bifurcation that occurred in CCM forward stage. Finally, experimental results are presented for verification purposes.

Adaptive Nonlinear Control of Multiphase Synchronous Buck Power Converters

The problem of controlling multiphase synchronous buck power converters is considered. The aim is to regulate the output voltage of the converter and to ensure an adequate current sharing between its different channels. The control law is designed from the large-signal bilinear model (of the whole multichannels converter) using the backstepping technique. The obtained regulator is shown to meet its objectives namely an asymptotic stability of the closed-loop system, a tight output voltage regulation, an adequate current sharing and a good estimation of load resistor.

ROBUST CONTROL OF INTERLEAVED SYNCHRONOUS PWM BUCK CONVERTERS

The problem of controlling interleaved buck power converters is considered. The aim is to regulate the output voltage of the converter and to ensure an adequate current sharing between its different channels. The control law is designed from the large-signal bilinear model (of the whole multi-channels converter) using the backstepping technique. The obtained regulator is shown to meet its objectives namely a tight output voltage regulation, a fast transient response, a good current sharing and robustness with respect to component uncertainties.

Slow-Scale Instability of Single-Stage Power-Factor-Correction Power Supplies

This paper reports slow-scale instability in a single-stage power-factor-correction (PFC) power supply, which is a popular design solution for low power applications. The circuit employs a cascade configuration of a boost converter and a forward converter, which share an active switch and operate in discontinuous-conduction mode (DCM), to provide input PFC and tight output regulation. Main results are given by "exact" cycle-by-cycle circuit simulations. The effect of the slow-scale instability on the attainable power factor is illustrated in terms of total harmonic distortion which can be found by taking the fast Fourier transform of the input current. The slow-scale instability usually manifests itself as local oscillations within a line cycle. Based on the critical condition of DCM for the buck converter, the underlying mechanism of such instability is further investigated. It has been found that border collision is the underlying cause of the phenomenon. Moreover, it has been shown that the border collision observed here is effectively a nonsmooth Neimark-Sacker bifurcation. Finally, experimental results are presented for verification purposes.

Single Phase Single Stage AC/DC Converter with High Input Power Factor and Tight Output Voltage Regulation

A single stage single switch AC/DC converter is an integration of input current shaper and a DC/DC cell with a shared controller and one active switch. The converter is applicable for digital input power supply with high input power factor and tight output voltage regulation. The focus of the topology is to reduce the DC bus voltage at light load without compromising with input power factor and voltage regulation. The concept behind this topology is direct power transfer scheme. Using special configuration of DC/DC cell does reduction of DC bus voltage and DC/DC cell works on the principle of series charging and parallel discharging. The power output of this converter can go up to 200W.