Ti Salicide Process Research Articles

Advanced salicided 4 Mbit flash memory array with borderless contacts

System on chip development requires many different devices to be integrated on the same chip and a high compatibility between CMOS logic core process and added modules. The self-aligned silicide process coming from high performance logic gives in a Flash memory array several opportunities: to take advantage of low word-line resistance, to eliminate any metal strap in the array reducing potential process defectivity thus improving devices yield. On the other hand, the salicidation of Flash memory requires at the same time to achieve a continuous low resistance line on the no-flat array topography (due to the double poly stacked gate memory cell structure) and to avoid any junction leakage risk, that might modify the device performances. The aim of this work is to demonstrate the feasibility and compatibility of advanced Ti salicide process with Flash memory array embedded in a high performance logic. The feasibility has been proven on a classical NOR 4 Mbit stand-alone memory test chip processed in 0.25 μm technology, that furthermore asks for borderless contacts.

A new and improved borderless contact (BLC) structure for high-performance Ti-salicide in sub-quarter micron CMOS devices

We demonstrate a new and improved borderless contact (BLC) Ti-salicide process for the fabrication of sub-quarter micron CMOS devices. A low-temperature chemical vapor deposition (CVD) SiO/sub x/N/sub y/ film to act as the selective etching stop layer and the additional n/sup +/ and p/sup +/ source-drain double implant structure (DIS) are employed in the studied device. The additional n/sup +/ and p/sup +/ DIS can reduce the junction leakage current, which is usually enhanced by BLC etching near the edge of shallow trench isolation (STI). The process window is enlarged. Furthermore, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration.

Effect of Mo doping on accelerated growth of C-54 TiSi2: Evidence for template mechanism

The phase sequence of the rapid thermal processing induced reaction at T=650 °C has been studied by a combination of high resolution transmission electron microscopy and image simulations. We found that pre-amorphization of poly-Si substrates does not change the reaction path, i.e., Ti5Si4 and C-49 TiSi2 phases were formed with the latter growing upon further annealing. In the Mo doped poly-Si/Ti system the C-54 TiSi2 phase forms along with Ti5Si4 and two Mo silicide phases, MoSi2 and Mo5Si3; no C-49 TiSi2 was observed. We provide direct evidence that the Ti–Si reaction in the Mo doped system follows the template mechanism with MoSi2 and Mo5Si3 based phases acting as template phases for accelerated growth of C-54 TiSi2. Direct formation of C-54 TiSi2 at lower temperatures bypassing C-49 TiSi2 is very promising for application of the Ti salicide process in the future generation of deep-submicron complementary metal–oxide–semiconductor devices.

A Novel Clean Ti Salicide Process Using Grooved Gate Structure

It is demonstrated that dry etching and Ar sputtering for Si surface cleaning cause phase transition failures of TiSi2 and degradation of the resistivity. We propose a Ti self-aligned-silicide (salicide) process using a grooved gate structure. In this technique, poly-Si is patterned by an oxide mask. The oxide layer protects the gate surface from contamination by dry etching for sidewall formation. Before Ti deposition, the poly-Si surface is not sputtered by Ar to clean the surface. As a result, TiSi2 agglomeration was suppressed drastically in comparison with the conventional gate structure.

Advanced salicides for 0.10 μm CMOS: Co salicide processes with low diode leakage and Ti salicide processes with direct formation of low resistivity C54 TiSi2

The scaling of CMOS technologies to 0.10 μm and beyond imposes increasingly demanding constraints to self-aligned silicide (salicide) processes. For high performance devices, it is essential that salicide processes achieve low gate and source-drain sheet resistance as well as low silicide to source-drain diffusion contact resistance, and maintain low junction leakage. This becomes increasingly difficult as junction depths and linewidths are scaled. In this paper we present an overview of the development of advanced Ti and Co salicide processes, with implementations into a high performance 0.10 μm complementary metal-oxide-semiconductor (CMOS) technology. For Co salicide, the main scaling issue is diode leakage on shallow junctions. We show that the use of pre-amorphization implants or a pre-Co deposition sputter etch improves diode leakage distributions, but fails to eliminate high leakage outliers. Co deposition temperature and rapid thermal processing (RTP) variables were found to have a strong effect on diode leakage, with optimization of either one resulting in tight low leakage distributions on shallow junctions. For conventional Ti salicide processes, the main scaling issue is sheet resistance on narrow lines due to incomplete high resistivity C49 TiSi2 to low resistivity C54 TiSi2 transformation. We present X-ray diffraction (XRD) and high resolution transmission electron microscopy (HRTEM) studies that indicate that direct growth of C54 TiSi2 bypassing the C49 phase is achieved at low temperatures on polycrystalline or amorphous Si with the addition of Mo impurities, eliminating the narrow line effect. The mechanism is demonstrated to be nucleation of MoSi2 and an unidentified phase at the Ti/Si interface, followed by epitaxial growth of C54 TiSi2 on these templates. Ti salicide processes with Mo impurities were evaluated, demonstrating an optimized one-step RTP process combining Mo and pre-amorphization implants that maintains low sheet resistance to 0.06 μm gate lengths. Successful implementations into a 0.10 μm flow were achieved both for optimized Co salicide or Ti salicide processes.

Comparative evaluation of Ti salicide and Co salicide processes for CMOS devices

Optimized Ti salicide and Co salicide module processes were comparatively evaluated. The pre-amorphization process and Si intermixing process for TiSi2 formation were effective methods for maintaining low sheet resistance in narrow regions. However, in the case of the Si intermixing process, the threshold voltage of PMOS devices was unstable. With the pre-amorphization process for Ti salicide, a stable threshold voltage was obtained in CMOS devices. In addition, a low sheet resistance in the narrow regions was maintained in the Co salicide process, without the pre-amorphization process. In the contact process, CoSi2 was not easily etched off by the dry etching gas used for contact hole formation. By using the optimized pretreatment method with low sputtering yield, Co salicide will have wider process windows than Ti salicide. © 1998 Scripta Technica, Electron Comm Jpn Pt 2, 81(8): 26–31, 1998

A low thermal budget self-aligned Ti silicide technology using germanium implantation for thin-film SOI MOSFET's

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET's is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET's such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-/spl mu/m SOI MOSFET's are fabricated with good device characteristics.

Scaled CMOS technologies with low sheet resistance at 0.06-μm gate lengths

A novel Ti self-aligned silicide (salicide) process using a combination of low dose molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06-μm gate lengths (mean=5.2 /spl Omega//sq, max=5.7 /spl Omega//sq at 0.07 μm; mean=6.7 /spl Omega//sq, max=8.1 /spl Omega//sq at 0.06 μm, TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thickness on S/D=38 nm), in contrast with previous Ti salicide processes which failed below 0.10 μm. The process was successfully implemented into a 1.5 V, 0.12-μm CMOS technology achieving excellent drive currents (723 and 312 μA/μm at I/sub OFF/=1 nA/μm for nMOS and pMOS, respectively).

Low Temperature Formation of C54 TiSi2 Bypassing the C49 Phase: Effect of Si Crystallinity, Metallic Impurities and Applications TO 0.10 μm CMOS

ABSTRACTThe mechanism and evolution from the early stages of the Ti/Si reaction by rapid thermal processing (RTP) at 650°C in the presence of Mo doping was studied and compared to the case without Mo doping; for amorphous, polycrystalline and single crystal (100) Si substrates. It was found that for Mo doped polycrystalline Si or Mo doped amorphous Si, the low resitivity C54 TiSi2 phase nucleates at the Ti/Si interface and grows following diffusion limited kinetics, bypassing the nucleation of the high resistivity C49 TiSi2 phase. The conventional phase sequence, with C49 TiSi 2 nucleation and growth, was observed on Mo doped (100) Si and all samples without Mo. The mechanism of early C54 nucleation was identified by high resolution transmission electron microscopy (HRTEM): at early stages of the reaction, precursor silicide phases lattice matched to C54 TiSi2 nucleate at the Ti/Mo doped Si interface, and act as templates for epitaxial nucleation of C54 TiSi2. Two such phases were observed, MoSi2 and a phase with spacings of 2.26 Å and 4.2 Å. Image simulations suggest that the structure of the second template phase is based on Mo5Si3. Similar kinetics were observed on large structures and narrow lines for Mo doped Si (except for the case of (100) Si), indicating that this growth mechanism eliminates the linewidth dependence. Implementation on a 0.10 μm CMOS technology of a process combining Mo doping with pre-amorphization (PAI) achieves low source/drain (S/D) sheet resistance, and the first Ti salicide process with low gate sheet resistance down to 0.06 μm.

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm Cmos

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm CMOS

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

CoSi 2 and TiSi 2 for [formula omitted] heterodevices

Novel Si SiGe heterodevices with enhanced performance demand low thermal budget contact formation. CoSi 2 and TiSi 2 can meet this requirement. The investigation of self-aligned rapid thermal processes for the formation of CoSi 2 (at 600–650 °C) and TiSi 2 (at 650–750 °C) and their application to n-channel hetero field effect transistors and heterobipolar transistors (HBTs) is described and effects on the device performance are presented. Specific resistances of around 20 μΩ cm for CoSi 2 and 17 μΩ cm for TiSi 2 could be confirmed for the Si/SiGe heterosystem. Contact resistances on n +-phosphorous implanted layers below 6 μΩ cm 2 have been derived from TLM structures. The silicide formation is severely affected by SiGe. Therefore the compound formation of CoSi 2 in the Co Si and the Co Si 1 − xGe x system has been investigated and compared as a function of annealing time in a temperature range from 400 to 600 °C. X-ray diffraction measurements on SiGe layers confirmed the formation of a mixture of CoSi and Co germanides with higher resistivity due to the interfacial reaction and the accumulation of Ge at the interface, which may act as a diffusion barrier. The choice of a Si cap above SiGe, whose thickness was properly adjusted to the material consumption correlated with the resulting silicide thickness, is proposed. The process and the performance of SiGe HBTs could be improved by the introduction of a Ti salicide process: base resistances yield values around 20 Ω (for an emitter area of 0.8 × 5 μm 2). Nearly ideal Gummel plots confirm the advantage of using TiSi 2.

Ti-Salicide Improvement by Preamorphization for ULSI Applications

AbstractTo improve Ti SALICIDE process, Si preamorphization by arsenic before Ti sputtering has been studied in two parts: process characterization and fundamental studies. Sheet resistance (Rs) reduction by the preamorphization is more pronounced on thinner and narrower-line silicide formation. At 60keV implantation energy, there is an optimum arsenic dose for the improvement. Through the treatment, more uniform silicide layer can be formed, indicated by the improved Rs uniformity. In the fundamental study, preamorphization appears to have little effect on promoting C49-to-C54 phase transformation. It is suggested that the treatment is able to enhance the reaction rate between Ti and amorphous Si, and results in C54-TiSi2 with larger grains and consequently slightly lower resistivity.

Application of Cobalt Salicide in Sub-Quarter Micron Ulsi

AbstractA thin Ti-siuicide film is widely used today as the low resistance shunt in a semiconductor chip. As the feature size in the chip shrinks to sub-quarter micron, the thin Ti-silicide film formed on such narrow lines transforms from C49 to C54 at increasing temperatures and agglomerates at decreasing temperatures, closing the process window for Ti-salicide process. In contrast, low resistivity Co-silicide thin films can be formed on narrow lines below the agglomeration temperature. In addition, an epitaxial CoSi2 with a flat interface can be formed in source/drain areas, enabling the formation of very shallow junctions with low leakage current. Experimental results on formation of silicides from Co/Ti bilayers and thermal stability of the CoSi2 films will be presented, with special emphasis on the sheet resistance of the silicide film versus poly-line width down to 0.15 umn. Interaction between dopants and silicide films will also be discussed.

Direct determination of process latitude for titanium salicide formation

A new quantitative method is presented to determine the sensitivity of the Ti salicide process to the de-oxidation step before the metal deposition. 0.7 μm CMOS production-type wafers have been processed for this step in a system allowing controlled chemical oxide bevelling along a wafer diameter. The wafers then went through all the subsequent processing steps of an industrial process including electrical testing. Results obtained on various electrical test patterns are discussed, and information about the salicide process window is presented.